The effect of trapped charge distributions on data retention characteristics of NAND Flash memory cells

IEEE Electron Device Letters

Volumn 28, Issue 8, 2007, Pages 750-752

  Park, Mincheol ^a   Suh, Kangdeog ^a   Kim, Keonsoo ^a   Hur, Sung Hoi ^a   Kim, Kinam ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Data retention; Endurance; NAND Flash memory; Narrow width effect; Tunnel oxide

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRON TRAPS; NAND CIRCUITS; TRANSISTORS;

DATA RETENTION; NAND FLASH MEMORY; SHALLOW-TRENCH ISOLATION; TUNNEL OXIDE;

FLASH MEMORY;

EID: 34547819223     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.901271     Document Type: Article

References (13)

1. F. Arai, T. Maruyama, and R. Shirota, "Extended data retention process technology for highly reliable flash EEPROM's of 106 to 107 W/E cycles," in Proc. IRPS, 1998, pp. 378-382.
2. Y. Manabe, K. Okuyama, K. Kubota, A. Nozoe, T. Karashima, K. Ujiie, H. Kanno, M. Nakashima, and N. Ajika, "Detailed observation of small leak current in flash memories with thin tunnel oxides," IEEE Trans. Semicond. Manuf., vol. 12, no. 2, pp. 170-174, Feb. 1999.
3. H. Watanabe, K. Shimizu, Y. Takeuchi, and S. Aritome, "Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories," in IEDM Tech. Dig., 1996, pp. 833-836.
4. H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Keme, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, and K. Ogura, "A new data retention mechanism after endurance stress on flash memory," in Proc. IRPS, 2000, pp. 194-199.
5. H. P. Belgal, N. Rihos, I. Kalastirsky, J. Peterson, R. Shiner, and N. Mielke, "A new reliability model for post-cycling retention of flash memories," in Proc. IRPS, 2002, pp. 7-20.
6. F. Schuler, R. Degraeve, P. Hendrickx, and D.Wellekens, "Physical charge transport models for anomalous leakage current in floating gate-based nonvolatile memory cells," IEEE Trans. Device Mater. Rel. vol. 2, no. 4, pp. 80-88, Dec. 2002.
7. J. D. Lee, J. H. Choi, D. G. Park, and K. Kim, "Data retention characteristics of sub-100 nm NAND flash memory cells," IEEE Electron Device Lett., vol. 24, no. 12, pp. 748-750, Dec. 2003.
8. S. S. Chung and T. C. Li, "An analytical threshold-voltage model of trench isolated MOS devices with nonuniformly doped substrates," IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 614-622, Mar. 1992.
9. A. Ghetti, A. Benvenuti, G. Molteni, S. Alberici, V. Soncini, and A. Pavan, "Experimental and simulation study of boron segregation and diffusion during gate oxidation and spike annealing," in IEDM Tech. Dig., 2004, pp. 983-986.
10. J. H. Park, S. H. Hur, J. H. Lee, J. T. Park, J. S. Sel, J.W. Kim, S. B. Song, J. Y. Lee, J. H. Lee, S. J. Son, Y. S. Kim, M. C. Park, S. J. Chai, J. D. Choi, U. I. Chung, J. T. Moon, K. T. Kim, K. Kim, and B. I. Yoo, "8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology," in IEDM Tech. Dig., 2004, pp. 873-876.
11. H.-S. Oh, S.-C. Lee, C.-S. Lee, D.-Y. Oh, T.-K. Kim, J.-H. Song, K.-H. Lee, Y.-K. Park, J.-H. Choi, and J.-T. Kong, "3-dimensional analysis on the cell string current of NAND flash memory," in Proc. Non-Volatile Memory Technol. Symp., 2005, pp. 7-10.
12. K. F. Schuegraf and C. Hu, "Hole injection oxide breakdown model for very low voltage lifetime extrapolation," in Proc. IRPS, 1993, pp. 7-12.
13. G. Bursuker, Y. Jeon, and H. R. Huff, "Degradation of thin oxide during electrical stress," Microelectron. Reliab., vol. 41, no. 12, pp. 1923-1931, Dec. 2001.