-
1
-
-
25144514874
-
Modeling and sizing for minimum energy operation in subthreshold circuits
-
Sep.
-
B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
-
(2005)
IEEE J. Solid-state Circuits
, vol.40
, Issue.9
, pp. 1778-1786
-
-
Calhoun, B.1
Wang, A.2
Chandrakasan, A.3
-
2
-
-
0031212817
-
Supply and threshold voltage scaling for low power CMOS
-
Aug.
-
R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, Issue.8
, pp. 1210-1216
-
-
Gonzalez, R.1
Gordon, B.M.2
Horowitz, M.A.3
-
3
-
-
80052901671
-
Design trade-offs in ultra-low-power digital nanoscale CMOS
-
Mar.
-
A. Tajalli and Y. Leblebici, "Design trade-offs in ultra-low-power digital nanoscale CMOS," IEEE Trans. Circuits Syst. I, vol. PP, no. 99, pp. 1-12, Mar. 2011.
-
(2011)
IEEE Trans. Circuits Syst. I
, vol.PP
, Issue.99
, pp. 1-12
-
-
Tajalli, A.1
Leblebici, Y.2
-
4
-
-
2442716234
-
A 180 mV FFT processor using sub-threshold circuit techniques
-
A. Wang and A. Chandrakasan, "A 180 mV FFT processor using sub-threshold circuit techniques," in IEEE ISSCC Dig., 2004, pp. 292-295.
-
(2004)
IEEE ISSCC Dig.
, pp. 292-295
-
-
Wang, A.1
Chandrakasan, A.2
-
5
-
-
0742286681
-
Ultra-low-power DLMS adaptive filter for hearing aid applications
-
Dec.
-
C. Kim, H. Soeleman, and K. Roy, "Ultra-low-power DLMS adaptive filter for hearing aid applications," IEEE Trans. VLSI Syst., vol. 11, no. 6, pp. 1058-1067, Dec. 2003.
-
(2003)
IEEE Trans. VLSI Syst.
, vol.11
, Issue.6
, pp. 1058-1067
-
-
Kim, C.1
Soeleman, H.2
Roy, K.3
-
6
-
-
68549090734
-
Energy efficient subthreshold processor design
-
Aug.
-
B. Zhai et al., "Energy efficient subthreshold processor design," IEEE Trans. VLSI Syst., vol. 17, no. 8, pp. 1127-1137, Aug. 2009.
-
(2009)
IEEE Trans. VLSI Syst.
, vol.17
, Issue.8
, pp. 1127-1137
-
-
Zhai, B.1
-
7
-
-
70449707767
-
Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits
-
D. Bol et al., "Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits," in Proc. ISLPED, 2009, pp. 21-26.
-
(2009)
Proc. ISLPED
, pp. 21-26
-
-
Bol, D.1
-
8
-
-
75649141765
-
Ultralow-power design in near-threshold region
-
Feb.
-
D. Markovic et al., "Ultralow-power design in near-threshold region," Proc. IEEE, vol. 98, no. 2, pp. 237-252, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 237-252
-
-
Markovic, D.1
-
9
-
-
4444374513
-
Theoretical and practical limits of dynamic voltage scaling
-
B. Zhai et al., "Theoretical and practical limits of dynamic voltage scaling," in Proc. ACM/IEEE DAC, 2004, pp. 868-873.
-
(2004)
Proc. ACM/IEEE DAC
, pp. 868-873
-
-
Zhai, B.1
-
10
-
-
75649093754
-
Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
-
Feb.
-
R. G. Dreslinski et al., "Near-threshold computing: Reclaiming Moore's law through energy efficient integrated circuits," Proc. IEEE, vol. 98, no. 2, pp. 253-266, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 253-266
-
-
Dreslinski, R.G.1
-
11
-
-
36949010083
-
Energy efficient near-threshold chip multi-processing
-
B. Zhai et al., "Energy efficient near-threshold chip multi-processing," in Proc. ISLPED, 2007, pp. 32-37.
-
(2007)
Proc. ISLPED
, pp. 32-37
-
-
Zhai, B.1
-
12
-
-
47849095115
-
An energy efficient parallel architecture using near threshold operation
-
Romania
-
R. Dreslinski et al., "An energy efficient parallel architecture using near threshold operation," in Proc. IEEE PACT, Romania, 2007, pp. 175-185.
-
(2007)
Proc. IEEE PACT
, pp. 175-185
-
-
Dreslinski, R.1
-
13
-
-
70349294336
-
An ultra-low-energy/frame multi-standard JPEG co-processor in 65 nm CMOS with sub/near-threshold power supply
-
Y. Pu et al., "An ultra-low-energy/frame multi-standard JPEG co-processor in 65 nm CMOS with sub/near-threshold power supply," in IEEE ISSCC Dig., 2009, pp. 146-147.
-
(2009)
IEEE ISSCC Dig.
, pp. 146-147
-
-
Pu, Y.1
-
14
-
-
74049111485
-
Energy-performance tunable logic
-
B. Nezamfar et al., "Energy-performance tunable logic," in Proc. IEEE CICC, 2009, pp. 183-186.
-
(2009)
Proc. IEEE CICC
, pp. 183-186
-
-
Nezamfar, B.1
-
15
-
-
0013277474
-
An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique
-
S. Sakiyama et al., "An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique," in IEEE ISSCC Dig., 1999, pp. 156-158.
-
(1999)
IEEE ISSCC Dig.
, pp. 156-158
-
-
Sakiyama, S.1
-
16
-
-
34047191904
-
A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications
-
Apr.
-
S. Zhou and Gabriel, "A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications," IEEE Trans. Circuits Syst., vol. 53, no. 4, pp. 319-323, Apr. 2006.
-
(2006)
IEEE Trans. Circuits Syst.
, vol.53
, Issue.4
, pp. 319-323
-
-
Zhou, S.1
Gabriel2
-
17
-
-
33947393602
-
Power-supply circuits for ultralow-power sub-threshold MOS-LSIs
-
Nov.
-
T. Hirose et al., "Power-supply circuits for ultralow-power sub-threshold MOS-LSIs," IEICE Electronics Express, vol. 3, no. 22, pp. 464-468, Nov. 2006.
-
(2006)
IEICE Electronics Express
, vol.3
, Issue.22
, pp. 464-468
-
-
Hirose, T.1
-
18
-
-
33751394434
-
Post-placement voltage Island generation under performance requirement
-
H. Wu et al., "Post-placement voltage island generation under performance requirement," IEEE/ACM ICCAD, pp. 309-316, 2005.
-
(2005)
IEEE/ACM ICCAD
, pp. 309-316
-
-
Wu, H.1
-
19
-
-
34250765870
-
Timing-constrained and voltage-Island-aware voltage assignment
-
H. Wu et al., "Timing-constrained and voltage-island-aware voltage assignment," ACM/IEEE DAC, pp. 429-432, 2006.
-
(2006)
ACM/IEEE DAC
, pp. 429-432
-
-
Wu, H.1
-
20
-
-
34547274187
-
Improving voltage assignment by outlier detection and incremental placement
-
H. Wu and M. Wong, "Improving voltage assignment by outlier detection and incremental placement," ACM/IEEE DAC, pp. 459-464, 2007.
-
(2007)
ACM/IEEE DAC
, pp. 459-464
-
-
Wu, H.1
Wong, M.2
-
21
-
-
0036911921
-
Managing power and performance for system-on-chip designs using voltage Islands
-
D. E. Lackey et al., "Managing power and performance for system-on-chip designs using voltage islands," ACM/IEEE ICCAD, pp. 195-202, 2002.
-
(2002)
ACM/IEEE ICCAD
, pp. 195-202
-
-
Lackey, D.E.1
-
22
-
-
16244400467
-
Architecting voltage Islands in core-based system-on-a-chip designs
-
J. Hu, "Architecting voltage islands in core-based system-on-a-chip designs," Proc. ISLPED, pp. 180-185, 2004.
-
(2004)
Proc. ISLPED
, pp. 180-185
-
-
Hu, J.1
-
23
-
-
49749150981
-
Process variation tolerant pipeline design through a placement-aware multiple voltage Island design style
-
D. Bertozzi, S. Bonesi, L. Benini, and E. Macii, "Process variation tolerant pipeline design through a placement-aware multiple voltage island design style," ACM/IEEE DATE, pp. 967-972, 2008.
-
(2008)
ACM/IEEE DATE
, pp. 967-972
-
-
Bertozzi, D.1
Bonesi, S.2
Benini, L.3
Macii, E.4
-
24
-
-
70449930713
-
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
-
A. Ghosh et al., "A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation," Proc. ISLPED, pp. 45-50, 2009.
-
(2009)
Proc. ISLPED
, pp. 45-50
-
-
Ghosh, A.1
-
25
-
-
84864570157
-
Multi-threshold CMOS digital circuits
-
Norwell, MA: Kluwer
-
M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits, Managing Leakage Power. Norwell, MA: Kluwer, 2003.
-
(2003)
Managing Leakage Power
-
-
Anis, M.1
Elmasry, M.2
-
26
-
-
2442466161
-
A leakage reduction methodology for distributed MTCMOS
-
May
-
B. H. Calhoun et al., "A leakage reduction methodology for distributed MTCMOS," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 818-826, May 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.5
, pp. 818-826
-
-
Calhoun, B.H.1
-
28
-
-
37749025732
-
Nanometer MOSFET variation in minimum energy subthreshold circuits
-
Jan.
-
N. Verma et al., "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 163-174, Jan. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.1
, pp. 163-174
-
-
Verma, N.1
-
30
-
-
39749127776
-
Design-time optimization of post-silicon tuned circuits using adaptive body bias
-
Mar.
-
S. Kulkarni, D. Sylvester, and D. Blaauw, "Design-time optimization of post-silicon tuned circuits using adaptive body bias," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 27, no. 3, pp. 481-494, Mar. 2008.
-
(2008)
IEEE Trans. Computer-aided Design Integr. Circuits Syst.
, vol.27
, Issue.3
, pp. 481-494
-
-
Kulkarni, S.1
Sylvester, D.2
Blaauw, D.3
-
31
-
-
79957712619
-
A resolution sub-threshold based digital process-sensing circuit in 45 nm CMOS
-
May
-
B. Datta and W. Burleson, "A resolution sub-threshold based digital process-sensing circuit in 45 nm CMOS," in Proc. ACM Great Lakes Symp. VLSI, GLSVLSI, May 2011, pp. 133-138.
-
(2011)
Proc. ACM Great Lakes Symp. VLSI, GLSVLSI
, pp. 133-138
-
-
Datta, B.1
Burleson, W.2
-
32
-
-
58149218298
-
RazorII: In situ error detection and correction for PVT and SER tolerance
-
Jan.
-
S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. Blaauw, "RazorII: In situ error detection and correction for PVT and SER tolerance," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 32-48, Jan. 2009.
-
(2009)
IEEE J. Solid-state Circuits
, vol.44
, Issue.1
, pp. 32-48
-
-
Das, S.1
Tokunaga, C.2
Pant, S.3
Ma, W.-H.4
Kalaiselvan, S.5
Lai, K.6
Bull, D.M.7
Blaauw, D.8
-
33
-
-
49549118719
-
A completely digital on-chip circuit for local random variability measurement
-
Feb
-
R. Rao, K. Jenkins, and J. Kim, "A completely digital on-chip circuit for local random variability measurement," in IEEE ISSCC Dig., Feb. 2008, pp. 412-623.
-
(2008)
IEEE ISSCC Dig.
, pp. 412-623
-
-
Rao, R.1
Jenkins, K.2
Kim, J.3
-
34
-
-
85018033479
-
A high sensitivity process variation sensor utilizing subthreshold operation
-
Sep
-
M. Meterelliyoz, P. Song, F. Stellari, J. Kulkarni, and K. Roy, "A high sensitivity process variation sensor utilizing subthreshold operation," in Proc. IEEE CICC, Sep. 2008, pp. 125-128.
-
(2008)
Proc. IEEE CICC
, pp. 125-128
-
-
Meterelliyoz, M.1
Song, P.2
Stellari, F.3
Kulkarni, J.4
Roy, K.5
|