Process variation tolerant pipeline design through a placement-aware multiple voltage Island design style

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 967-972

  Stefano, Bonesi ^a   Bertozzi, Davide ^a   Benini, Luca ^c   Macii, Enrico ^b  

^a UNIVERSITY OF FERRARA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INDUSTRIAL ENGINEERING; LANDFORMS; NONMETALS; OPTICAL DESIGN; PIPELINES; SILICON; STATIC ANALYSIS; TESTING;

DESIGN TIME; DYNAMIC ADAPTATIONS; FABRICATED CHIPS; MULTIPLE VOLTAGES; NOVEL DESIGN METHODOLOGY; PERFORMANCE REQUIREMENTS; PIPELINE DESIGNS; POWER COSTS; POWER OVERHEAD; PROCESS VARIATIONS; PROMISING TECHNIQUE; SILICON TESTING; STATISTICAL STATIC TIMING ANALYSIS; SUPPLY VOLTAGES; VOLTAGE ISLANDS;

PROCESS ENGINEERING;

EID: 49749150981     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484806     Document Type: Conference Paper

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