Design trade-offs in ultra-low-power digital nanoscale CMOS

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 9, 2011, Pages 2189-2200

  Tajalli, Armin ^a,b   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

^b Kandou Technologies   (Switzerland)

Author keywords

CMOS integrated circuits; CMOS logic; digital CMOS circuits; energy consumption; noise margin; power delay product; subthreshold; ultra low power; weak inversion

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMERCE; DELAY CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; ENERGY UTILIZATION; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT DESIGN; MOS DEVICES; NANOTECHNOLOGY; PREDICTIVE ANALYTICS; RELIABILITY ANALYSIS; THRESHOLD VOLTAGE;

CMOS LOGIC; DIGITAL CMOS; NOISE MARGINS; POWER DELAY PRODUCT; SUBTHRESHOLD; ULTRA LOW POWER; WEAK INVERSIONS;

LOW POWER ELECTRONICS;

EID: 80052901671     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2112595     Document Type: Article

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