A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 45-50

  Ghosh, Amlan ^a   Rao, Rahul M ^b   Brown, Richard B ^a  

^a UNIVERSITY OF UTAH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Fine grain body biasing; Process variation compensation; Slewrate

Indexed keywords

65NM TECHNOLOGY; BIAS CONTROL; BODY BIAS; BODY BIASING; CENTRALIZED CONTROL SYSTEMS; COMPENSATION TECHNIQUES; CRITICAL PATH DELAYS; DESIGN CONSIDERATIONS; FREQUENCY OF OPERATION; MOS-FET; MULTIPLE REGIONS; OPERATING POINTS; OPTIMAL POWER; PARAMETRIC YIELD; PERFORMANCE CHARACTERISTICS; PROCESS VARIATION; SEMICONDUCTOR MANUFACTURING; SIMULATION RESULT; SLEW-RATE; SUPPLY VOLTAGES; TOTAL POWER; WITHIN-DIE PROCESS;

DIES; LOW POWER ELECTRONICS; POWER ELECTRONICS;

DESIGN;

EID: 70449930713     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594245     Document Type: Conference Paper

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