Energy-performance tunable logic

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 183-186

  Nezamfar, Bita ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC TOPOLOGIES; IN-FIELD; INTERCONNECT CIRCUITS; LOGIC FAMILIES; PERFORMANCE TUNING; POST-FABRICATION; POWER SUPPLY; STATIC CIRCUIT; SYSTEM REQUIREMENTS; TEST CHIPS;

INTEGRATED CIRCUITS;

LOGIC CIRCUITS;

EID: 74049111485     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280874     Document Type: Conference Paper

References (6)

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2. A. Solomatnikov, D. Somasekhar, N. Sirisantana, K. Roy, "Skewed CMOS: Noise-tolerant high-performance low-power static circuit family", IEEE Transactions on Very Large Scale Integration Systems, 2002
3. V. George, H. Zhang and J. Rabaey, "The design of a low energy FPGA," International Symposium on Low power Electronics and Design, 1999.
4. D. Patil, et al, "A new method for design of robust digital circuits," Proc. International Symposium on Quality Electronic Design, March 2005.
5. Quarry from www.chipworks.com on a recent FPGA chip.
6. R. Ho, et al, "Applications of on-chip samplers for test and measurement of integrated circuits", VLSI, 1998.