Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 253-266

  Dreslinski, Ronald G ^a   Wieckowski, Michael ^a   Blaauw, David ^a   Sylvester, Dennis ^a   Mudge, Trevor ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

CMOS integrated circuits; Computer architecture; Energy conservation; Parallel processing; VLSI

Indexed keywords

BUDGET CONTROL; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ENERGY CONSERVATION; ENERGY EFFICIENCY; ENERGY UTILIZATION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; THRESHOLD VOLTAGE; TIMING CIRCUITS; VOLTAGE SCALING;

ENERGY EFFICIENT; NEAR-THRESHOLD COMPUTING; PARALLEL PROCESSING; PERFORMANCE PENALTIES; REDUCE ENERGY CONSUMPTION; SUB-THRESHOLD DESIGN; SUBTHRESHOLD OPERATION; VLSI;

COMPUTER CIRCUITS;

EID: 75649093754     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2034764     Document Type: Article

References (51)

1. G. Moore, "No exponential is forever: But Fforever- can be delayed!" in Proc. IEEE Int. Solid-State Circuits Conf., 2003, Keynote address.
2. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm p-channel FinFET, "IEEE Trans. Electron Devices, pp. 880-886, May 2001.
3. A. W. Topol, J. D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, "Three-dimensional integrated circuits, "IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491-506, Jul./Sep. 2006.
4. BReport to congress on server and data center energy efficiency, "U.S. Environmental Protection Agency.
5. [Online]. Available: http://www.energystar.gov/ia/partners/prod- development/downloads/EPA- Datacenter-Report-Congress-Final1.pdf
6. R. Swanson and J. Meindl, "Ion-implanted complementary MOS transistors in low-voltage circuits, "IEEE J. Solid-State Circuits, vol.7, no.2, pp. 146-153, 1972.
7. S. Hanson, ". Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. Das, W. Haensch, E. Nowak, and D. Sylvester, "Ultra low-voltage, minimum energy CMOS, "IBM J. Res. Develop., pp. 469-490, Jul./Sep. 2006.
8. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operations, "IEEE J. Solid-State Circuits, vol.12, no.3, pp. 224-231, 1977.
9. R. Lyon and C. Mead, "An analog electronic cochlea, "Trans. Acoust, Speech, Signal Process., vol.36, no.7, pp. 1119-1134, 1988.
10. C. Mead, Analog VLSI and Neural Systems. Boston, MA: Addison-Wesley, 1989.
11. H. Soeleman and K. Roy, "Ultra-low power digital subthreshold logic circuits, "in Proc. ACM/IEEE Int. Symp. Low Power Electronics Design, 1999, pp. 94-96.
12. B. Paul, H. Soeleman, and K. Roy, BAn 8x8 sub-threshold digital CMOS carry save array multiplier, "in Proc. IEEE Eur. Solid-State Circuits Conf., 2001.
13. C. Kim, H. Soeleman, and K. Roy, BUltra-low-power DLMS adaptive filter for hearing aid applications, "IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 1058-1067, 2003.
14. A. Wang and A. Chandrakasan, "A 180 mV FFT processor using subthreshold circuit techniques, "in Proc. IEEE Int. Solid-State Circuits Conf., 2004, pp. 292-529.
15. B. Calhoun and A. Chandrakasan, "A 256 kb sub-threshold SRAM in 65 nm CMOS, "in Proc. IEEE Int. Solid-State Circuits Conf., 2006, pp. 628-629.
16. B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, "A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency, "in IEEE Symp. VLSI Circuits, 2006, pp. 154-155.
17. [Online]. Available: http://www.transmeta.com/
18. [Online]. Available: http://www.intel.com/design/intelxscale/
19. IBM PowerPC.
20. [Online]. Available: http://www.chips.ibm.com/products/powerpc/
21. B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, "Theoretical and practical limits of dynamic voltage scaling, "in Proc. Design Automation Conf, Jan. 1, 2004, pp. 868-873.
22. S. Hanson, ". Zhai, M. Seok, ". Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. Blaauw, "Performance and variability optimization strategies in a sub-200 mV, 3.5 pJ/inst, 11 nW subthreshold processor, "in Symp. VLSI Circuits, 2007, pp. 152-153.
23. M. Seok, S. Hanson, Y. Lin, Z. Foo, D. Kim, Y. Lee, N. Liu, D. Sylvester, and D. Blaauw, "The phoenix processor: A 30 pW platform for sensor applications, "in IEEE Symp. VLSI Circuits, 2008, pp. 188-189.
24. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture, "in Proc. ACM/IEEE Design Automation Conf., 2003, pp. 338-343.
25. B. Zhai, R. Dreslinski, T. Mudge, D. Blaauw, and D. Sylvester, "Energy efficient near-threshold chip multi-processing, "in Proc. ACM/IEEE Int. Symp. Low-Power Electronics Design, 2007, pp. 32-37.
26. R. Dreslinski, B. Zhai, T. Mudge, D. Blaauw, and D. Sylvester, "An energy efficient parallel architecture using near threshold operation, "in Parallel Architectures and Compilation Techniques (PACT), Sep. 2007.
27. B. Paul, A. Raychowdhury, and K. Roy, "Device optimization for ultra-low power digital sub-threshold operation, "in Proc. Int. Symp. Low Power Electronics and Design, 2004, pp. 96-101. (Pubitemid 40454692)
28. N. Checka, J. Kedzierski, and C. Keast, "A subthreshold-optimized FDSOI technology for ultra low power applications, "in Proc. GOMAC, 2008.
29. S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, "Nanometer device scaling in subthreshold circuits, "in Proc. Design Automation Conf., 2007, pp. 700-705.
30. M. Wieckowski, Y. Park, C. Tokunaga, D. Kim, Z. Food, D. Sylvester, and D. Blaauw, "Timing yield enhancement through soft edge flip-flop based design, "in Proc. IEEE Custom Integrated Circuts Conf. (CICC), Sep. 2008.
31. V. Joshi, D. Blaauw, and D. Sylvester, "Soft-edge flip-flops for improved timing yield: Design and optimization, "in Proc. Int. Conf. Comput.-Aided Design, 2007, pp. 667-673.
32. G. Gammie, A. Wang, M. Chau, S. Gururajarao, R. Pitts, F. Jumel, S. Engel, P. Royannez, R. Lagerquist, H. Mair, J. Vaccani, G. Baldwin, K. Heragu, R. Mandal, M. Clinton, D. Arden, and K. Uming, BA 45 nm 3.5 G baseband-and-multimedia application processor using adaptive body-bias and ultra-low-power techniques, "in Proc. Int. Solid-State Circuits Conf., 2008.
33. B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200 mV 6 T SRAM in 130 nm CMOS, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2007.
34. L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3 GHz 8 T-SRAM with operation down to 0.41 V in 65 nm CMOS, "in IEEE Symp. VLSI Circuits, 2007, pp. 252-253.
35. B. Calhoun and A. Chandrakasan, BA 256 kb Sub-threshold SRAM in 65 nm CMOS, "in Int. Solid-State Circuits Conf., 2006, pp. 259-260.
36. G. K. Chen, D. Blaauw, T. Mudge, D. Sylvester, and N. S. Kim, "Yield-driven near-threshold SRAM design, "in Int. Conf. Comput.-Aided Design, 2007, pp. 660-666.
37. R. Dreslinski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester, and K. Flautner, "Reconfigurable energy efficient near threshold cache architectures, "in Proc. 41st Annu. MICRO, 2008.
38. IDC's Worldwide Installed Base Forecast, 2007-2010. Framingham, MA: IDC, Mar. 2007. IDC.
39. R. Katz, "Research directions in internet-scale computing, "in Proc. 3rd Int. Week Management of Networks and Services, 2007, Keynote presentation.
40. [Online]. Available: http://www.spec.org/web2005
41. T. Pering, T. Burd, and R. Brodersen, BThe simulation and evaluation of dynamic voltage scaling algorithms, "in Proc. ACM/IEEE Int. Symp. Low Power Electronics Design, 1998, pp. 76-81.
42. L. Bircher and L. John, "Power phases in a commercial server workload, "in Proc. Int. Symp. Low Power Electronics and Design, 2006.
43. L. Nazhandali, M. Minuth, ". Zhai, J. Olson, T. Austin, and D. Blaauw, "A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution, "in ACM/IEEE Int. Conf. Compilers, Archit., Synthesis Embedded Syst., 2005.
44. M. Elgebaly and M. Sachdev, "Efficient adaptive voltage scaling system through on-chip critical path emulation, "in Proc. Int. Symp. Low Power Electronics and Design, 2004, pp. 375-380.
45. A. Raychowdhury, S. Ghosh, and K. Roy, "A novel on-chip delay measurement hardware for efficient speed-binning, "in Proc. Int. On-Line Testing Symp., 2005, pp. 287-292.
46. B. H. Calhoun and A. P. Chandrakasan, "Standby power reduction using dynamic voltage scaling and canary flip-flop structures, "IEEE J. Solid-State Circuits, vol.39, pp. 1504-1511, 2004.
47. T. Kehl, "Hardware self-tuning and circuit performance monitoring, "in Proc. IEEE Int. Conf. Computer Design, 1993, pp. 188-192.
48. T. Sato and Y. Kunitake, "A simple flip-flop circuit for typical-case designs for DFM, "in Proc. Int. Symp. Quality Electronic Design, 2007, pp. 539-544.
49. T. Austin, V. Bertacco, D. Blaauw, and T. Mudge, "Opportunities and challenges for better than worst-case design, "in Proc. Asia South Pacific Design Automation Conf., 2005, pp. 2-7.
50. T. Austin, D. Blaauw, T. Mudge, and K. Flautner, "Making typical silicon matter with Razor, "IEEE Comput., vol.37, pp. 57-65, 2004.
51. S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, "A self-tuning DVS processor using delay-error detection and correction, "IEEE J. Solid-State Circuits, vol.41, no.4, pp. 792-804, Apr. 2006.