Three-dimensional wafer stacking using Cu-Cu bonding for simultaneous formation of electrical, mechanical, and hermetic bonds

IEEE Transactions on Device and Materials Reliability

Volumn 12, Issue 2, 2012, Pages 194-200

  Tan, Chuan Seng ^a   Peng, Lan ^a   Fan, Ji ^a   Li, Hongyu ^b   Gao, Shan ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Cu Cu bonding; hermetic seal; three dimensional integrated circuit (3 D IC)

Indexed keywords

3-D INTEGRATION; ELECTRICAL CONNECTION; HELIUM LEAK RATE; MECHANICAL SUPPORT; MIL-STD-883E; OHMIC BEHAVIOR; SIMULTANEOUS FORMATION; THREE DIMENSIONAL INTEGRATED CIRCUITS; UNDERFILLS; WAFER CURVATURE; WAFER LEVEL; WAFER STACKING;

ELECTRIC CONNECTORS; HELIUM; HERMETIC SEALS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 84862123039     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2012.2188802     Document Type: Article

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