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3D Hyper-Integration and Packaging Technologies for Micro-Nano-Systems
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January
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Proceedings of The IEEE
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Lu, J.-Q.1
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P. Garrou, P. Ramm, and C. Bower, editors, Wiley-VCN, May
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P. Garrou, P. Ramm, and C. Bower, editors, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Wiley-VCN, May 2008.
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Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits
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3
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70449620692
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3D Integration Based upon Dielectric Adhesive Bonding
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eds, C.S. Tan, R.J. Gutmann, and R. Reif, pp, Springer
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J.-Q. Lu, T.S. Cale and R.J. Gutmann, "3D Integration Based upon Dielectric Adhesive Bonding", in Wafer Level 3-D ICs Process Technology, eds., C.S. Tan, R.J. Gutmann, and R. Reif, pp. 219-256, Springer, 2008.
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Wafer Level 3-D ICs Process Technology
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Lu, J.-Q.1
Cale, T.S.2
Gutmann, R.J.3
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4
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33645536175
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F. Niklaus, G. Stemme, J.-Q. Lu, and R. Gutmann, Adhesive Wafer Bonding, Journal of Applied Physics (Applied Physics Review - Focused Review), 99, Issue 3, pp. 031101-1-28, Feb. 1, 2006.
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F. Niklaus, G. Stemme, J.-Q. Lu, and R. Gutmann, "Adhesive Wafer Bonding," Journal of Applied Physics (Applied Physics Review - Focused Review), Vol. 99, Issue 3, pp. 031101-1-28, Feb. 1, 2006.
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5
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85001133965
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Stacked Chip-to-Chip Interconnections Using Wafer Bonding Technology with Dielectric Bonding Glues
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IEEE, June 4-6
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J.-Q. Lu, Y. Kwon, R.P. Kraft, R.J. Gutmann, J.F. McDonald, and T.S. Cale, "Stacked Chip-to-Chip Interconnections Using Wafer Bonding Technology with Dielectric Bonding Glues," 2001 IEEE International Interconnect Technology Conference (IITC 2001), pp. 219-221, IEEE, June 4-6, 2001.
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2001 IEEE International Interconnect Technology Conference (IITC 2001)
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Lu, J.-Q.1
Kwon, Y.2
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Cale, T.S.6
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6
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Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding
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eds, E. Zschech, C. Whelan, T. Mikolajick, pp, Springer-Verlag, August
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J.-Q. Lu, T.S. Cale, and R.J. Gutmann, "Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding," Materials for Information Technology: Devices. Interconnects and Packaging, eds., E. Zschech, C. Whelan, T. Mikolajick, pp. 386-397, Springer-Verlag, August 2005.
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Materials for Information Technology: Devices. Interconnects and Packaging
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Lu, J.-Q.1
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7
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33644812081
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Critical Adhesion Energy of Benzocyclobutene (BCB)-Bonded Wafers
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Y. Kwon, J. Seok, J.-Q. Lu, T.S. Cale and R.J. Gutmann, "Critical Adhesion Energy of Benzocyclobutene (BCB)-Bonded Wafers," Journal of The Electrochemical Society, 153 (4), pp. G347-G352 (2006).
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Journal of The Electrochemical Society
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J.-Q. Lu, K.W. Lee, Y. Kwon, G. Rajagopalan, J. McMahon, B. Altemus, M. Gupta, E. Eisenbraun, B. Xu, A. Jindal, R.P. Kraft, J.F. McDonald, J. Castracane, T.S. Cale, A. Kaloyeros, and R.J. Gutmann, Processing of Inter-Wafer Vertical Interconnects in 3D ICs, Advanced Metallization Conference in 2002 (AMC 2002), pp. 45-51, eds., B.M. Melnick, T.S. Cale, S. Zaima, and T. Ohta, MRS Proc. VI8. 2003.
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J.-Q. Lu, K.W. Lee, Y. Kwon, G. Rajagopalan, J. McMahon, B. Altemus, M. Gupta, E. Eisenbraun, B. Xu, A. Jindal, R.P. Kraft, J.F. McDonald, J. Castracane, T.S. Cale, A. Kaloyeros, and R.J. Gutmann, "Processing of Inter-Wafer Vertical Interconnects in 3D ICs," Advanced Metallization Conference in 2002 (AMC 2002), pp. 45-51, eds., B.M. Melnick, T.S. Cale, S. Zaima, and T. Ohta, MRS Proc. Vol. VI8. 2003.
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9
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77955186942
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Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs
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June
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J.-Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, M. Rasco, R. Augur, T.S. Cale, and R.J. Gutmann, "Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs," 2003 IEEE International Interconnect Technology Conference (IITC 2003), pp. 74-76, June 2003.
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2003 IEEE International Interconnect Technology Conference (IITC 2003)
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Lu, J.-Q.1
Jindal, A.2
Kwon, Y.3
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Augur, R.6
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Gutmann, R.J.8
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10
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A Wafer-Level 3D IC Technology Platform
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R.J. Gutmann, J.-Q. Lu, S. Pozder, Y. Kwon, D. Menke, A. Jindal, M. Celik, M. Rasco, J.J. McMahon, K. Yu, and T.S. Cale, "A Wafer-Level 3D IC Technology Platform," Advanced Metallization Conference in 2003 (AMC 2003), pp. 19-26, 2003.
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Back-End Compatibility of Bonding and Thinning Processes for a Wafer-Level 3D Interconnect Technology Platform/
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June
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S. Pozdcr, J.-Q. Lu, Y. Kwon, S. Zollner, J. Yu, J.J. McMahon, T.S. Cale, K. Yu, and R.J. Gutmann, "Back-End Compatibility of Bonding and Thinning Processes for a Wafer-Level 3D Interconnect Technology Platform/' IEEE International Interconnect Technology Conference (IITC 2004), pp. 102-104, June 2004.
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Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits,
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Dec
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K.-N. Chen, S.H. Lee, P.S. Andry, C.K. Tsang, A.W. Topol, Y.-M. Lin, J.-Q. Lu, A.M. Young, M. Icong, and W. Haensch, "Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits,"' Technical Digest of IEEE International Electron Devices Meeting (2006IEDM), pp. 367-370, Dec. 2006.
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K.N. Chen, C.K. Tsang, A.W. Topol, S.H. Lee, B.K. Furman, D.L. Rath, J.-Q. Lu, A.M. Young, S. Purushothaman, and W. Haensch, "Improved Manufacturability of Cu Bond Pads and Implementation of Seal Design in 3D Integrated Circuits and Packages", in 23rd International VLSI Multilevel Interconnection (VMIC) Conference, ed., T. Wade, pp. 195-202, IMIC, September 2006.
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