Three-dimensional wafer stacking via Cu - Cu bonding integrated with 65-nm strained-Si/Low-k CMOS technology

IEEE Electron Device Letters

Volumn 27, Issue 5, 2006, Pages 335-337

  Morrow, Patrick R ^a   Park, C M ^a   Ramanathan, S ^a   Kobrinsky, M J ^a   Harmes, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CMOS; Copper bonding; Through silicon vias (TSVs); Wafer stacking

Indexed keywords

BONDING; MOSFET DEVICES; SEMICONDUCTING SILICON; STATIC RANDOM ACCESS STORAGE; WSI CIRCUITS;

COPPER BONDING; THROUGH-SILICON-VIAS; WAFER STACKING;

CMOS INTEGRATED CIRCUITS;

EID: 33646236322     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.873424     Document Type: Article

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