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Electrochemical and Solid-State Letters

Volumn 8, Issue 6, 2005, Pages

Silicon multilayer stacking based on copper wafer bonding

(2) Tan, C S a Reif, R a

a Massachusetts Institute of Technology Cambridge (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; COPPER; MULTILAYERS; OXIDES; SCANNING ELECTRON MICROSCOPY; SILICON ON INSULATOR TECHNOLOGY; SOLUTIONS; STACKING FAULTS; TEMPERATURE DISTRIBUTION;

COPPER WAFER; DEVICE LAYERS; SILICON SUBSTRATES; THREE-DIMENSIONAL (3D) INTEGRATION;

SILICON;

EID: 20844460644 PISSN: 10990062 EISSN: None Source Type: Journal
DOI: 10.1149/1.1904506 Document Type: Article

Times cited : (69)

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