Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments

Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics

Volumn 30, Issue 2, 2012, Pages

  Krzeminski, Christophe D ^a  

^a Institut Superieur de l'Electronique et du Numerique   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC DEVICES; NANOTECHNOLOGY; STRESS CONCENTRATION;

45NM TECHNOLOGY; ELECTRICAL PERFORMANCE; ETCH STOP; EXPERIMENTAL STUDIES; FABRICATION PROCESS; GLOBAL TRENDS; NANOSCALE DEVICE; P-TYPE; PROCESS SIMULATIONS; PROCESSING STEPS; SEMICONDUCTOR COMPANIES; STRAIN ENGINEERING; STRESS ENGINEERING; STRESS FIELD; TRANSISTOR CHANNELS;

ENGINEERING RESEARCH;

EID: 84861601372     PISSN: 21662746     EISSN: 21662754     Source Type: Journal    
DOI: 10.1116/1.3683079     Document Type: Article

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