High-performance metal/high-κ n- and p-MOSFETs with top-cut dual stress liners using gate-last damascene process on (100) substrates

IEEE Transactions on Electron Devices

Volumn 56, Issue 4, 2009, Pages 620-626

  Mayuzumi, Satoru ^a,b   Yamakawa, Shinya ^a   Tateshita, Yasushi ^a   Hirano, Tateshita ^a   Nakata, Masashi ^a   Yamaguchi, Shinpei ^a   Tai, Kaori ^a   Wakabayashi, Hitoshi ^a   Tsukamoto, Masanori ^a   Nagashima, Naoki ^a  

^a SONY CORPORATION   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

Channel stress; Damascene gate; Electron mobility; Embedded SiGe (eSiGe); Gate last; HfO2; HfSix; High ; Hole mobility; Metal gate; Replacement gate; Stress simulation; TiN; Top cut stress liner

Indexed keywords

CHANNEL STRESS; DAMASCENE GATE; EMBEDDED SIGE (ESIGE); GATE LAST; HFO2; HFSIX; METAL GATE; REPLACEMENT GATE; STRESS SIMULATION;

ELECTRON MOBILITY; HAFNIUM COMPOUNDS; LOGIC GATES; METAL RECOVERY; MOSFET DEVICES; SEMICONDUCTING GERMANIUM COMPOUNDS; SEMICONDUCTING SILICON COMPOUNDS; SILICON ALLOYS; SILICON NITRIDE; SUBSTRATES; TENSILE STRESS; TITANIUM COMPOUNDS; TITANIUM NITRIDE;

HOLE MOBILITY;

EID: 67349246511     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2014192     Document Type: Article

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