Analyzing strained-silicon options for stress-engineering transistors

Solid State Technology

Volumn 47, Issue 7, 2004, Pages 49-52

  Moroz, Victor ^a   Xu, Xiaopeng ^a   Pramanik, Dipu ^a   Nouri, Faran ^b   Krivokapic, Zoran ^c  

^a SYNOPSYS INC   (United States)

^b APPLIED MATERIALS INC   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STRAINED SILICON; STRESS ENGINEERING; TRADEOFFS; VIRTUAL PROCESS FLOWS;

CARRIER MOBILITY; COMPUTATIONAL GEOMETRY; COMPUTER SIMULATION; DEPOSITION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MOSFET DEVICES; OXIDATION; SEMICONDUCTOR DEVICES; STRESS CONCENTRATION; STRESSES; TENSILE STRESS;

SILICON;

EID: 3242712428     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (6)

1. C.S. Smith, "Piezoresistance Effect in Germanium and Silicon," Phys. Rev., Vol. 94, No. 1, pp. 42-49, 1954.
2. S.E. Thompson, et al., "A Logic Nanotechnology Featuring Strained-silicon," IEEE Electron Dev. Lett., Vol. 25, No. 4, pp. 191-193, 2004.
3. V. Moroz, et al" "Modeling the Impact of Stress on Silicon Processes and Devices," Mat. Sci. in Semicond. Processing, Vol. 6, pp. 27-36, 2003.
4. T. Ghani, et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," Proc. IEDM, pp. 978-980, 2003.
5. Z. Krivokapic, et al., "Locally Strained Ultra-thin Channel 25nm Narrow FDSOI Devices with Metal Gate and Mesa Isolation," Proc. IEDM, pp. 445-448, 2003.
6. M.V. Fischetti, S.E. Laux,"Band Structure, Deformation Potentials, and Carrier Mobility in Strained Si, Ge, and SiGe Alloys," J. Appl. Phys., Vol. 80, p. 2234, 1996.