A 90-nm logic technology featuring strained-silicon

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1790-1797

  Thompson, Scott E ^a   Armstrong, Mark ^a   Auth, Chis ^a   Alavi, Mohsen ^a   Buehler, Mark ^a   Chau, Robert ^a   Cea, Steve ^a   Ghani, Tahir ^a   Glass, Glenn ^a   Hoffman, Thomas ^a   Jan, Chia Hong ^a   Kenyon, Chis ^a   Klaus, Jason ^a   Kuhn, Kelly ^a   Ma, Zhiyong ^a   Mcintyre, Brian ^a   Mistry, Kaizad ^a   Murthy, Anand ^a   Obradovic, Borna ^a   Nagisetty, Ramune ^a   Nguyen, Phi ^a   Sivakumar, Sam ^a   Shaheed, Reaz ^a   Shifren, Lucian ^a   Tufts, Bruce ^a   Tyagi, Sunit ^a   Bohr, Mark ^a   El Mansy, Youssef ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPRESSIVE STRESS; COPPER; ELECTRON MOBILITY; HOLE MOBILITY; NICKEL COMPOUNDS; SEMICONDUCTING SILICON; SILICON NITRIDE; STRAIN; VLSI CIRCUITS;

LOGIC TECHNOLOGY; NANOSCALE TRANSISTOR; PIEZORESISTANCE COEFFICIENTS; STRAINED SILICON; TENSILE STRAIN;

MOSFET DEVICES;

EID: 8344236776     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.836648     Document Type: Article

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