A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip

ACM Journal on Emerging Technologies in Computing Systems

Volumn 8, Issue 1, 2012, Pages

  Ye, Yaoyao ^a   Xu, Jiang ^a   Wu, Xiaowen ^a   Zhang, Wei ^b   Liu, Weichen ^a   Nikdast, Mahdi ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Hierarchical architecture; Multiprocessor system on chip; Optical network on chip; Optical electronic router; Power consumption

Indexed keywords

ADAPTIVE POWER CONTROL; AVERAGE PACKET DELAYS; CAPACITY UTILIZATION; COMMUNICATION LOCALITY; CONTROL PROTOCOLS; CYCLE ACCURATE; FLOOR-PLANNING; FLOORPLANS; HARDWARE COST; HIERARCHICAL ARCHITECTURES; LASER SOURCES; LOW POWER; LOW-LATENCY; LOW-POWER CONSUMPTION; MULTIPROCESSOR SYSTEM ON CHIPS; MULTIPROCESSOR SYSTEMS ON CHIPS; NETWORK ON CHIP; NETWORK THROUGHPUT; NETWORKS ON CHIPS; ON CHIP COMMUNICATION; OPTICAL COMMUNICATION TECHNOLOGIES; OPTICAL ELECTRONICS; OPTICAL NETWORK-ON-CHIP; OPTICAL ROUTERS; OPTICAL SWITCHING; POWER EFFICIENCY; ULTRA-HIGH BANDWIDTH; UNIFORM TRAFFIC;

ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FIBER OPTIC NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTICAL COMMUNICATION; SERVERS; VLSI CIRCUITS;

ROUTERS;

EID: 84859070066     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/2093145.2093150     Document Type: Article

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