FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2010, Pages

  Pan, Yan ^a   Kim, John ^b   Memik, Gokhan ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; NANOPHOTONICS; NETWORK ARCHITECTURE; SUPERCOMPUTERS;

CROSSBAR ARCHITECTURE; ELECTRICAL POWER CONSUMPTION; ENERGY EFFICIENT; MANY-CORE ARCHITECTURE; NETWORK THROUGHPUT; ON-CHIP NETWORKS; OPTICAL CHANNELS; STATIC POWER CONSUMPTION;

COMPUTER ARCHITECTURE;

EID: 77952560573     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.2010.5416626     Document Type: Conference Paper

References (26)

1. 2007 International Technology Roadmap for Semiconductors(ITRS).
2. V. Almeida, C. Barrios, R. Panepucci, M. Lipson, M. Foster, D. Ouzounov, and A. Gaeta. All-optical switching on a silicon chip. Optics Letters, 29:2867-2869, 2004.
3. J. Balfour and W. J. Dally. Design tradeoffs for tiled CMP on-chip networks. In Proc. of the Int'l Conference on Supercomputing (ICS), pages 187-198, Carns, Queensland, Australia, 2006.
4. C. A. Barrios, V. R. Almeida, and M. Lipson. Low-power-consumption short-length and high-modulation-depth silicon electro-optic modulator. Journal of Lightwave Technology, 21(4):1089-1098, 2003.
5. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic. Building manycore processor-to-dram networks with monolithic silicon photonics. In Proc. of Hot Interconnects, pages 21-30, Stanford, CA, 2008.
6. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. Mackay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook. Tile64 processor: A 64-core soc with mesh interconnect. In Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE Int'l, pages 88-598, 2008.
7. C.-S. Chang, D.-S. Lee, and C.-M. Lien. Load balanced Birkhoff-von Neumann switches with resequencing. In ACM SIGMETRICS Performance Evaluation Review, volume 29, 2001.
8. M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi. Phastlane: A rapid transit optical routing network. In Proc. of the Int'l Symposium on Computer Architecture (ISCA), Austin, TX, 2009.
9. W. J. Dally and T. B. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishing Inc., 2004.
10. R. Das, S. Eachempati, A. Mishra, V. Narayanan, and C. Das. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In Int'l Symposium on High-Performance Computer Architecture (HPCA), pages 175-186, Raleigh, NC, USA, Feb. 2009.
11. R. K. Dokania and A. B. Apsel. Analysis of challenges for on-chip optical interconnects. In GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI, pages 275-280, New York, NY, USA, 2009. ACM.
12. P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger. Implementation and evaluation of on-chip network architectures. In Int'l Conference on Computer Design (ICCD), pages 477-484, San Jose, CA, 2006.
13. A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic. Silicon-photonic clos networks for global on-chip communication. In IEEE Int'l Symposium on Network-on-Chip (NOCS), San Diego, CA, 2009.
14. N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In IEEE/ACM Int'l Symposium on Microarchitecture (MICRO), pages 492-503, Orlando, FL, 2006.
15. P. Kumar, Y. Pan, J. Kim, G. Memik, and A. Choudhary. Exploring concentration and channel slicing in on-chip network router. In IEEE Int'l Symposium on Network-on-Chip (NOCS), San Diego, CA, 2009.
16. M. M. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (gems) toolset. ACM SIGARCH Computer Architecture News, 33(4):92-99, Sep. 2005.
17. R. Narayanan, B. Ozisikyilmaz, J. Zambreno, G. Memik, and A. Choudhary. Minebench: A benchmark suite for data mining workloads. In IEEE Int'l Symposium on Workload Characterization (IISCW), pages 182-188, San Jose, CA, 2006.
18. Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary. Firefly: Illuminating future network-on-chip with nanophotonics. In Proc. of the Int'l Symposium on Computer Architecture (ISCA), Austin, TX, 2009.
19. L. Pavesi and D. J. Lockwood. Silicon Photonics, Volume 94 of Topics in applied physics. Springer-Verlag, 2004.
20. A. Shacham, K. Bergman, and L. P. Carloni. The case for low-power photonic networks-on-chip. In Proc. of Design Automation Conference (DAC), pages 132-135, San Diego, CA, 2007.
21. J. Tatum. Vcsels for 10 gb/s optical interconnects. In IEEE Emerging Technologies Symposium on BroadBand Communications for the Internet Era, pages 58-61, Richardson, TX, 2001.
22. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H.Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. An 80-Tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits, IEEE Journal of, 43(1):29-41, 2008.
23. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. L. Binkert, R. G. Beausoleil, and J. H. Ahn. Corona: System implications of emerging nanophotonic technology. In Proc. of the Int'l Symposium on Computer Architecture (ISCA), pages 153-164, Beijing, China, 2008.
24. H.-S.Wang, L.-S. Peh, and S. Malik. A power model for routers: Modeling alpha 21364 and infiniband routers. IEEE Micro, 23(1):26-35, 2003.
25. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. of the Int'l Symposium on Computer Architecture (ISCA), pages 24-36, Santa Margherita Ligure, Italy, Jun. 1995.
26. L. Zheng, A. Mickelson, L. Shang, M. Vachharajani, D. Filipovic, W. Park, and Y. Sun. Spectrum: A hybrid nanophotonic-electric onchip network. In Proc. of Design Automation Conference (DAC), San Francisco, CA, Jun 2009.