Predictions of CMOS compatible on-chip optical interconnect

Integration, the VLSI Journal

Volumn 40, Issue 4, 2007, Pages 434-446

  Chen, Guoqing ^a   Chen, Hui ^b   Haurylau, Mikhail ^a   Nelson, Nicholas A ^a   Albonesi, David H ^c   Fauchet, Philippe M ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

^b UNIVERSITY OF ROCHESTER   (United States)

^c School of Operations Research and Industrial Engineering   (United States)

Author keywords

CMOS compatible; On chip; Optical interconnect; Trends

Indexed keywords

BANDWIDTH; COPPER; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; UNCERTAINTY ANALYSIS;

CONVENTIONAL COPPER INTERCONNECT; ELECTRICAL INTERCONNECTS; ENVIRONMENTAL VARIATIONS; ON-CHIP OPTICAL INTERCONNECTS;

CMOS INTEGRATED CIRCUITS;

EID: 34249051162     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2006.10.001     Document Type: Article

References (54)

1. Goodman J.W., et al. Optical interconnects for VLSI systems. Proc. IEEE 72 7 (1984) 850-866
2. P. Kapur, K.C. Saraswat, Comparisons between electrical and optical interconnects for on-chip signaling, in: Proceedings of the IEEE International Interconnect Technology Conference, June 2002, pp. 89-91.
3. Kobrinsky M.J., et al. On-chip optical interconnects. Intel Technol. J. 8 2 (2004) 129-141
4. O'Connor I., and Gaffiot F. On-chip optical interconnect for low-power. In: Macii E. (Ed). Ultra-Low Power Electronics and Design (2004), Kluwer, Dordrecht
5. G. Chen, et al., On-chip copper-based vs. optical interconnects: delay uncertainty, latency, power, and bandwidth density comparative predictions, in: Proceedings of the IEEE International Interconnect Technology Conference, June 2006, pp. 39-41.
6. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003.
7. Y.I. Ismail, E.G. Friedman, Sensitivity of interconnect delay to on-chip inductance, in: Proceedings of the IEEE International Symposium on Circuits and Systems, May 2000, pp. 403-406.
8. Adler V., and Friedman E.G. Repeater design to reduce delay and power in resistive interconnect. IEEE Trans. Circuits Syst. Part II 45 5 (1998) 607-616
9. P. Kapur, Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects, Ph.D. Dissertation, Stanford University, Stanford, California, 2002.
10. Ismail Y.I., and Friedman E.G. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 8 2 (2000) 195-206
11. N.H. Mahmoud, Y.I. Ismail, Accurate rise time and overshoots estimation in RLC interconnects, in: Proceedings of the IEEE International Symposium on Circuits and Systems, May 2003, pp. 477-480.
12. Chen G., and Friedman E.G. Low power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 14 2 (2006) 161-172
13. El-Moursy M.A., and Friedman E.G. Optimum wire sizing of RLC interconnect with repeaters. Integration VLSI J. 38 2 (2004) 205-225
14. Ho R., Mai K.W., and Horowitz M.A. The future of wires. Proc. IEEE 89 4 (2001) 490-504
15. Chen L.H., Marek-Sadowska M., and Brewer F. Buffer delay change in the presence of power and ground noise. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 11 3 (2003) 461-473
16. Agrawal G.P. Fiber-Optic Communication Systems (1997), Wiley, New York
17. Soref R.A., and Bennett B.R. Electrooptical effects in silicon. IEEE J. Quantum Electron. 23 1 (1987) 123-129
18. Xu Q., et al. Micrometer-scale silicon electro-optic modulator. Nature 435 (2005) 325-327
19. Liu A., et al. A high-speed silicon optical modulator based on a metal-oxide-semiconductor capacitor. Nature 427 (2004) 615-618
20. Liao L., et al. High speed silicon Mach-Zehnder modulator. Opt. Express 13 8 (2005) 3129-3135
21. Barrios C.A., Almeida V.R., and Lipson M. Low-power-consumption short-length and high-modulation-depth silicon electrooptic modulator. J. Lightwave Technol. 21 4 (2003) 1089-1098
22. Weiss S.M., Molinari M., and Fauchet P.M. Temperature stability for silicon-based photonic band-gap structures. Appl. Phys. Lett. 83 10 (2003) 1980-1982
23. M. Haurylau, et al., Closed-form model of a capacitor-based electro-optical modulator, IEEE Trans. Electron Devices (2006), in press.
24. Cherkauer B.S., and Friedman E.G. A unified design methodology for CMOS tapered buffers. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 3 1 (1995) 99-111
25. Hedenstierna N., and Jeppson K.O. Cmos circuit speed and buffer optimization. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 6 2 (1987) 270-281
26. Sakurai T., and Newton A.R. Alpha-power law mosfet model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25 2 (1990) 584-594
27. Boyraz O., and Jalali B. Demonstration of a silicon raman laser. Opt. Express 12 21 (2004) 5269-5273
28. M. Haurylau, et al., Optical interconnect roadmap: challenges and critical directions, IEEE J. Sel. Top. Quantum Electron. (2006), in press.
29. Vlasov Y.A., and McNab S.J. Losses in single-mode silicon-on-insulator strip waveguides and bends. Opt. Express 12 8 (2004) 1622-1631
30. Eldada L., and Shacklette L.W. Advances in polymer integrated optics. IEEE J. Sel. Top. Quantum Electron. 6 1 (2000) 54-68
31. Averine S.V., Chan Y.C., and Lam Y. Geometry optimization of interdigitated schottky-barrier metal-semiconductor-metal photodiode structures. Solid-State Electron. 45 3 (2001) 441-446
32. Oh J., et al. Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers. IEEE J. Quantum Electron. 38 9 (2002) 1238-1241
33. Buca D., et al. Metal-germanium-metal ultrafast infrared detectors. J. Appl. Phys. 92 12 (2002) 7599-7605
34. Oh J., Banerjee S.K., and Campbell J. Metal-germanium-metal photodetectors on heteroepitaxial Ge-on-Si with amorphous Ge Schottky barrier enhancement layers. IEEE Photonics Technol. Lett. 15 5 (2003) 745-747
35. Pavesi L., and Lockwood D.J. Silicon Photonics (2004), Springer, New York
36. Chou S.Y., and Liu Y. 32 GHz metal-semiconductor-metal photodetector on silicon. Appl. Phys. Lett. 61 15 (1992) 1760-1762
37. Morikuni J.J., et al. Improvements to the standard theory for photoreceiver noise. J. Lightwave Technol. 12 4 (1994) 1174-1184
38. Yang B., et al. 10-Gb/s all-silicon optical receiver. IEEE Photonics Technol. Lett. 15 5 (2003) 745-747
39. Ajami A.H., Banerjee K., and Pedram M. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 24 6 (2005) 849-861
40. P. Friedberg, et al., Modeling within-die spatial correlation effects for process-design co-optimization," in: Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2005, pp. 516-521.
41. Cao Y., et al. Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 10 6 (2002) 799-805
42. Liu Z., et al. Threshold voltage model for deep-submicrometer MOSFET's. IEEE Trans. Electron Devices 40 1 (1993) 86-95
43. Niu G.F., Ruan G., and Chen R.M.M. Further comments on 'threshold voltage model for deep-submicrometer MOSFET's' and its extension to subthreshold operation. IEEE Trans. Electron Devices 43 12 (1996) 2311-2312
44. Arora N. MOSFET Models for VLSI Circuit Simulation-Theory and Practice (1993), Springer/Wien, NY
45. Einspruch N.G. VLSI Electronics Microstructure Science-Advanced MOS Device Physics (1989), Academic Press, San Diego, California
46. C.K. Hu, J.M.E. Harper, Copper interconnect: fabrication and reliability, in: Proceedings of the VLSI Technology, Systems, and Applications, June 1997, pp. 18-22.
47. Wong S., Lee G., and Ma D. Modeling of interconnect capacitance, delay, and crosstalk in VLSI. IEEE Trans. Semicond. Manuf. 13 1 (2000) 108-111
48. A.B. Kahng, S. Muddu, E. Sarto, On switch factor based analysis of coupled RC interconnects, in: Proceedings of the IEEE Great Lakes Symposium on VLSI, June 2000, pp. 79-84.
49. A.B. Kahng, et al., Interconnect tuning strategies for high-performance ICs, in: Proceedings of the IEEE Design, Automation and Test in Europe Conference, February 1998, pp. 471-478.
50. Ismail Y.I., and Friedman E.G. On the extraction of on-chip inductance. J. Circuits Syst. Comput. 12 1 (2003) 31-40
51. Cao Y., et al. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 13 9 (2005) 1072-1078
52. Y. Cao, et al., Design sensitivities to variability: extrapolation and assessments in nanometer VLSI, in: Proceedings of the IEEE ASIC/SOC Conference, September 2002, pp. 411-415.
53. V. Venkatraman, W. Burleson, Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations, in: Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2005, pp. 522-527.
54. Soljacic M., et al. Photonic-crystal slow-light enhancement of nonlinear phase sensitivity. J. Opt. Soc. Am. B 19 9 (2002) 2052-2059