Corona: System implications of emerging nanophotonic technology

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 153-164

  Vantrease, Dana ^a   Schreiber, Robert ^b   Monchiero, Matteo ^b   Mclaren, Moray ^b   Jouppi, Norman P ^b   Fiorentino, Marco ^b   Davis, Al ^c   Binkert, Nathan ^b   Beausoleil, Raymond G ^b   Ahn, Jung Ho ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH REQUIREMENTS; CORE MICROPROCESSORS; DENSE WAVELENGTH DIVISION MULTIPLEXING; ELECTRICAL SIGNALLING; ENERGY COSTS; GLOBAL WIRES; I/O DEVICES; INTER-CORE COMMUNICATION; INTERCONNECT POWER; INTERNATIONAL SYMPOSIUM; LOW POWERS; MEMORY BANDWIDTHS; MEMORY MODULES; MULTI-THREADED; ORDERS-OF-MAGNITUDE; PHOTONIC; POWER LEVELING; REDUCING POWER; SYSTEM IMPLICATIONS;

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; MICROPROCESSOR CHIPS; MULTIPLEXING; NONMETALS; SILICON; TECHNOLOGY; TELECOMMUNICATION SYSTEMS;

BANDWIDTH;

EID: 52649100126     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.35     Document Type: Conference Paper

References (35)

1. Proceedings of the ISSCC Workshop F2: Design of 3D-Chipstacks. IEEE, Feb 2007. Organizers: W. Weber and W. Bowhill.
2. ANSI/IEEE. Local. Area Networks: Token. Ring Access Method and Physical. Layer Specifications, Std 802.5. Technical report, 1989.
3. K. Asanovic, et al. The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, Dec 2006.
4. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4), Jul/Aug 2006.
5. M.-C. F. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher, and S.-W. Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. In HPCA, Feb 2008.
6. H. J. Chao, K.-L. Deng, and Z. Jing. A Petabit Photonic Packet Switch (P3S). In INFOCOM, 2003.
7. S. Chaudhry, P. Caprioli, S. Yip, and M. Tremblay. High-Performance Throughput Computing. IEEE Micro, 25(3), May/Jun 2005.
8. J. Choi, H. Lee, H. Hong, H. Kim, K. Kim, and H. Kim. Distributed optical, contention, resolution using an optical token-ring. Photonics Technology Letters, IEEE, 10(10), Oct 1998.
9. W. Dally and C. Seitz. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. IEEE Transactions on Computers, C-36(5), May 1987.
10. R. Drost, R. Hopkins, R. Ho, and I. Sutherl and Proximity Communication. JSSC, 39(9), Sep 2004.
11. A. Falcon, P. Faraboschi, and D. Ortega. Combining Simulation, and Virtualization through Dynamic Sampling. In ISPASS, Apr 2007.
12. Intel. Intel Atom Processor, http://www.intel.com/technology/atom.
13. _. Introducing the 45nm Next Generation Intel Core Microarchitecture. http://www.intel.com/technology/magazine/45nm/coremicroarchitecture-0507.htm.
14. N. E. Jerger, L.-S. Peh, and M. H. Lipasti. Virtual Circuit Tree Multicasting: A Case for On-CMp Hardware Multicast Support. ISCA, Jun 2008.
15. N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi. Leveraging Optical. Technology in Future Bus-based Chip Multiprocessors. In MICRO, 2006.
16. B. R. Koch, A. W. Fang, O. Cohen, and J. E. Bowers. Mode-locked silicon evanescent lasers. Optics Express, 15(18), Sep 2007.
17. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded Sparc Processor. IEEE Micro, 25(2), 2005.
18. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. Express Virtual. Channels: Towards the Ideal. Interconnection. Fabric. In ISCA, Jun 2007.
19. R. Kumar, V. Zyuban, and D. M. Tullsen. Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. In ISCA, Jun 2005.
20. M. Lipson. Guiding, Modulating, and Emitting Light on Silicon-Challenges and Opportunities. Journal of Lightwave Technology, 23(12), Dec 2005.
21. A. Louri and A. K. Kodi. SYMNET: An Optical Interconnection Network for Scalable High-Performance Symmetric Multiprocessors. Applied Optics, 42(17), Jun 2003.
22. M. M. K. Martin, D. J. Sorin, M. D. Hill, and D. A. Wood. Bandwidth Adaptive Snooping. In HPCA, Feb 2002.
23. N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda. Analysis and Design of Inductive Coupling and Transceiver Circuit for Inductive Inter-Chip Wireless Superconnect. JSSC, 40(4), Apr 2005.
24. U. Nawathe, M. Hassan, L. Warriner, K. Yen, B. Upputuri, D. Greenhill, A. Kumar, and H. Park. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. In ISSCC, Feb 2007.
25. R. Palmer, J. Poulton, W. J. Dally, J. Eyles, A. M. Fuller, T. Greer, M. Horowitz, M. Kellam, F. Quan, and F. Zarkeshvarl. A 14mW 6.25Gb/s Transceiver in 90nm. CMOS for Serial Chip-to-Chip Communications. In ISSCC, Feb 2007.
26. L. Schares, et al. Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies. IEEE Journal of Selected Topics in Quantum Electronics, 12(5), Sep/Oct 2006.
27. Semiconductor Industries Association. International Technology Roadmap for Semiconductors, http://www.itrs.net/, 2006 Update.
28. A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni. Photonic NoC for DMA Communications in Chip Multiprocessors. In IEEE Hot Interconnects, Aug 2007.
29. M. B. Taylor, et al. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In ISCA, Jun 2004.
30. S. Thoziyoor, N. Muralimanohar, J. Ahn, and N. P. Jouppi. CACTI 5.1. Technical Report HPL-2008-20, HP Labs.
31. S. Vangal, et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. In ISSCC, Feb 2007.
32. B. Webb and A. Louri. All-Optical Crossbar Switch Using Wavelength Division Multiplexing and Vertical-Cavity Surface-Emitting Lasers . Applied Optics, 38(29), Oct 1999.
33. _. A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. TPDS, 11(5), 2000.
34. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA, Jun 1995.
35. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson. Micrometre-scale silicon electro-optic modulator. Nature, 435, May 2005.