Phastlane: A rapid transit optical routing network

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 441-450

  Cianchetti, Mark J ^a   Kerekes, Joseph C ^a   Albonesi, David H ^a  

^a Department of Obstetrics Gynecology   (United States)

Author keywords

Interconnection networks; Multicore; Nanophotonics; Optical interconnects

Indexed keywords

CHIP PERFORMANCE; CMOS COMPATIBLE; ELECTRICAL CONTROL; GLOBAL INTERCONNECTS; GLOBAL WIRES; KEY COMPONENT; LOW-LATENCY; MULTI CORE; NETWORK POWER; ON-CHIP OPTICAL INTERCONNECTS; OPTICAL ROUTING; PROCESSING CORE; ROUTING NETWORKS; SIGNALING NETWORKS; SINGLE-CLOCK-CYCLE; SOURCE ROUTING;

COMPUTER ARCHITECTURE; COMPUTERS; INTEGRATED OPTICS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NANOPHOTONICS; NETWORK PERFORMANCE; OPTICAL INTERCONNECTS; PHOTONICS; RAPID TRANSIT; SIGNALING; SYSTEMS ENGINEERING;

ARTS COMPUTING;

EID: 70450230786     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555809     Document Type: Conference Paper

References (24)

1. V. R. Almeida, C. A. Barrios, R. R. Panepucci, M. Lipson, M. A. Foster, D. G. Ouzounov, and A. L. Gaeta. All-Optical Switching on a Silicon Chip. Optics Letters, 29(24):2867-2869, 2004.
2. J. Balfour and William Dally. Design Tradeoffs for Tiled CMP On-Chip Networks. In International Conference on Supercomputing, June 2008.
3. W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets. Low-Loss, Low-Cross-Talk Crossings for Silicon-on-Insulator Nanophotonic Waveguides. Optics Letters, 32(19):2801-2803, 2007.
4. G. Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe Fauchet, Eby Friedman, and David Albonesi. Predictions of CMOS Compatible On-Chip Optical Interconnect. In Proceedings of the International Workshop on System Level Interconnect, April 2005.
5. W. Dally and B. Towles. Principles and Practices Of Interconnection Networks. Morgan Kaufmann, 2007.
6. N. E. Jerger, L.-S. Peh, and M. Lipasti. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. In Proc. 35th IEEE/ACM International Symposium on Computer Architecture, June 2008.
7. A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanović, and V. Stojanović. Silicon-Photonic Clos Networks for Global On-Chip Communication. In Third ACM/IEEE International Symposium on Networks-on-Chip, May 2009.
8. N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi. Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. In Proc. IEEE/ACM 39th Annual International Symposium on Microarchitecture, Dec. 2006.
9. A. Kumar, Li-Shiuan Peh, Partha Kundu, and Niraj Jha. Express Virtual Channels: Towards the Ideal Interconnection Fabric. In Proc. 34th IEEE/ACM International Symposium on Computer Architecture, June 2007.
10. R. Kumar, Dean Tullsen, and Norman Jouppi. Core Architecture Optimization for Heterogeneous Chip Multiprocessors. In Parallel Architectures and Compilation Techniques, Sept. 2006.
11. N. McKeown. The iSLIP Scheduling Algorithm for Input-Queued Switches. ACM Transactions on Networking, 7(2):188-201, 1999.
12. D. Miller. Rationale and Challenges for Optical Interconnects to Electronic Chips. Proceedings of the IEEE, 88(6):728-749, 2000.
13. M. Paniccia, V. Krutul, R. Jones, O. Cohen, J. Bowers, A. Fang, and H. Park. A Hybrid Silicon Laser. White Paper, Intel Corporation, 2006.
14. H. Park, Y. hao Kuo, A. W. Fang, R. Jones, O. Cohen, M. J. Paniccia, and J. E. Bowers. A Hybrid AlGaInAs-Silicon Evanescent Preamplifier and Photodetector. Optics Express, 15(21):13539-13546, 2007.
15. K. Preston, P. Dong, B. Schmidt, and M. Lipson. High-Speed All-Optical Modulation Using Polycrystalline Silicon Microring Resonators. Applied Physics Letters, 92(15):151104, 2008.
16. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. Sesc simulator. http://sesc.sourceforge.net, 2005.
17. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2008.
18. A. Shacham, Keren Bergman, and Luca Carloni. On the Design of a Photonic Network-on-chip. In First International Symposium on Networks-on-Chip, May 2007.
19. L. Shiuan Peh and William Dally. A Delay Model and Speculative Architecture for Pipelined Routers. In International Symposium on High-Performance Computer Architecture, Jan. 2001.
20. J. Tatum. VCSELs for 10 GB/s Optical Interconnects. Broadband Communications for the Internet Era Symposium Digest, 2001 IEEE Symposium on Emerging Technologies, Sept. 2001.
21. D. Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Normal Jouppi, Marco Fiorentino, A. David, Nathan Binkert, Raymond Beausoleil, and Jung Ho Ahn. Corona: System Implications of Emerging Nanophotonic Technology. In Proc. 35th IEEE/ACM International Symposium on Computer Architecture, June 2008.
22. T. Woodward and A. Krishnamoorthy. 1-Gb/s Integrated Optical Detectors and Receivers in Commercial CMOS Technologies. IEEE Journal on Selected Topics in Quantum Electronics, 5(2):146-156, 1999.
23. F. Xia, L. Sekaric, and Y. Vlasov. Ultracompact Optical Buffers on a Silicon Chip. Nature Photonics, 1:65-71, 2006.
24. Q. Xu and M. Lipson. All-Optical Logic Based on Silicon Micro-Ring Resonators. Optics Express, 15(3):924-929, 2007.