Power comparison between high-speed electrical and optical Interconnects for inter-chip communication

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 116-118

  Cho, Hoyeol ^a   Kapur, Pawan ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; MODULATORS; OPTIMIZATION; PARAMETER ESTIMATION; SEMICONDUCTOR QUANTUM WELLS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; TRANSMITTERS;

CONTRAST RATIO (CR); INTER CHIP INTERFERENCE (ICI); INTERCONNECTS; POWER DISSIPATION;

POWER GENERATION;

EID: 8644235924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. P. Kapur et. al., Int. Interconnect Tech. Conf., pp. 224-226, 2003.
4. P. Kapur et. al., Int. Interconnect Tech. Conf., pp. 151-153, 2002
5. International Technology Roadmap for Semiconductor, 1999ed, San Jose, CA: Semiconductor Industry Association.
6. B. K. Casper et. al., Symp. VLSI circuits, pp. 54-57, 2002.
7. C. Svensson et. al., Trans. of Adv. Pkg., vol. 23, no. 2, pp. 191-196, 2001.
8. G. A. Keeler et. al., Optics in Computing, 2002.