Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors

Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

Volumn , Issue , 2009, Pages 129-136

  Bahirat, Shirish ^a   Pasricha, Sudeep ^a  

^a Department of Systems Engineering   (United States)

Author keywords

Chip multiprocessor; Network on chip; Photonic interconnect

Indexed keywords

ACCESS LATENCY; APPLICATION COMPLEXITY; CHIP MULTIPROCESSOR; HIGH BANDWIDTH; IN-PROCESS TECHNOLOGY; INTRA-CHIP COMMUNICATIONS; LARGE POWER; MASSIVELY PARALLEL SYSTEMS; NETWORKS ON CHIPS; NOC ARCHITECTURES; ON CHIPS; PHOTONIC INTERCONNECTS; PHOTONIC NETWORK; POWER CONSUMPTION; RING WAVEGUIDES; SCALABLE COMMUNICATION;

BIOLOGICAL MATERIALS; DATA TRANSFER; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS; TWO DIMENSIONAL;

EMBEDDED SYSTEMS;

EID: 72149085164     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629435.1629453     Document Type: Conference Paper

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