Impact of gate placement on RF power degradation in GaN high electron mobility transistors

Microelectronics Reliability

Volumn 52, Issue 1, 2012, Pages 33-38

  Joh, Jungwoo ^a   Del Alamo, Jesús A ^a  

^a Massachusetts Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DC STRESS; DEGRADATION BEHAVIOR; GAN HIGH ELECTRON MOBILITY TRANSISTORS; GATE DEVICES; GATE PLACEMENT; HIGH CURRENT STRESS; HIGH VOLTAGE; HIGH-POWER; HIGH-VOLTAGES; RF-POWER; SOURCE RESISTANCE; SOURCE-DRAIN; STRESS TEST;

DC POWER TRANSMISSION; DEGRADATION; ELECTRIC FIELDS; ELECTRON MOBILITY; ELECTRONIC EQUIPMENT TESTING; GALLIUM NITRIDE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 84155163070     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2011.09.008     Document Type: Conference Paper

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