SCOPUS 정보 검색 플랫폼

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

(13) Huang, Ru a Wang, Runsheng a Zhuge, Jing a Liu, Changze a Yu, Tao a Zhang, Liangliang a Huang, Xin a Ai, Yujie a Zou, Jinbin a Liu, Yuchao a Fan, Jiewen a Liao, Huailin a Wang, Yangyuan a

a PEKING UNIVERSITY (China)

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGNS; GATE-ALL-AROUND; HIERARCHICAL MODELING; NOISE CHARACTERISTIC; PARASITIC EFFECT; SCALED CMOS; SELF-HEATING EFFECT; SI NANOWIRE; SILICON NANOWIRE TRANSISTORS; SURROUNDING-GATE; TECHNOLOGY ROADMAPS; TRANSPORT BEHAVIOR;

CMOS INTEGRATED CIRCUITS; GALLIUM ALLOYS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; NANOWIRES; RELIABILITY ANALYSIS; THREE DIMENSIONAL;

ELECTRIC NETWORK ANALYSIS;

EID: 80455145051 PISSN: 08865930 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/CICC.2011.6055334 Document Type: Conference Paper

Times cited : (20)

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