FinFET performance advantage at 22nm: An AC perspective

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 12-13

  Guillorn, M ^a   Chang, J ^a   Bryant, A ^a   Fuller, N ^a   Dokumaci, O ^a   Wang, X ^a   Newbury, J ^a   Babich, K ^a   Ott, J ^a   Haran, B ^a   Yu, R ^a   Lavoie, C ^a   Klaus, D ^a   Zhang, Y ^a   Sikorski, E ^a   Graham, W ^a   To, B ^a   Lofaro, M ^a   Tornello, J ^a   Koli, D ^a   Yang, B ^a   Pyzyna, A ^a   Neumeyer, D ^a   Khater, M ^a   Yagishita, A ^a   Kawasaki, H ^a   Haensch, W ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

FinFET; Parasitic capacitance

Indexed keywords

CAPACITANCE; FIELD EFFECT TRANSISTORS;

FINFET; FINFETS; JUNCTION CAPACITANCES; PARASITIC CAPACITANCE; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 51949118252     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588544     Document Type: Conference Paper

References (2)

1. W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti, "Silicon CMOS devices beyond scaling," IBM J. Research & Development, vol. 50, pp. 339, 2006.
2. W. Wu, M. Chan, "Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs," IEEE Trans. Electron Devices, vol. 54, pp. 692-698, April, 2007.