A 32 GBit/s communication SoC for a waferscale neuromorphic system

Integration, the VLSI Journal

Volumn 45, Issue 1, 2012, Pages 61-75

  Scholze, Stefan ^a   Eisenreich, Holger ^a   Höppner, Sebastian ^a   Ellguth, Georg ^a   Henker, Stephan ^a   Ander, Mario ^a   Hänzsche, Stefan ^a   Partzsch, Johannes ^a   Mayr, Christian ^a   Schüffny, René ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Clock to data alignment; Configuration over AER; Gigaevent packet based AER; Low voltage differential signaling; Serial data transmission

Indexed keywords

CLOCK-TO-DATA ALIGNMENT; CONFIGURATION OVER AER; GIGAEVENT PACKET-BASED AER; LOW-VOLTAGE-DIFFERENTIAL- SIGNALING; SERIAL DATA TRANSMISSION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARTS COMPUTING; BANDWIDTH; COMMUNICATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NEURAL NETWORKS; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

TELECOMMUNICATION SYSTEMS;

EID: 80055001408     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2011.05.003     Document Type: Article

References (50)

1. T. Koickal, A. Hamilton, S. Tan, J. Covington, J. Gardner, and T. Pearce Analog VLSI circuit implementation of an adaptive neuromorphic olfaction chip IEEE Transactions on Circuits and Systems I: Regular Papers 54 2007 60 73 (Pubitemid 46351019)
2. S. Mitra, S. Fusi, and G. Indiveri Real-time classification of complex patterns using spike-based learning in neuromorphic VLSI IEEE Transactions on Biomedical Circuits and Systems 2009 32 42
3. H. Berge, P. Häfliger, High-speed serial AER on FPGA, in: ISCAS 2007, 2007, pp. 857860.
4. D. Fasnacht, A. Whatley, G. Indiveri, A serial communication infrastructure for multi-chip address event systems, in: ISCAS 2008, 2008, pp. 648651.
5. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares Barranco, and R.e.a. Paz-Vicente CAVIAR: A 45 k neuron, 5 M synapse, 12 G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking IEEE Transactions on Neural Networks 20 2009 1417 1434
6. J. Schemmel, D. Brüderle, A. Grübl, M. Hock, K. Meier, S. Millner, A wafer-scale neuromorphic hardware system for large-scale neural modeling, in: ISCAS 2010, 2010, pp. 19471950.
7. J. Schemmel, K. Meier, E. Mueller, A new VLSI model of neural microcircuits including spike time dependent plasticity, in: IEEE International Joint Conference on Neural Networks, IJCNN 2004, vol. 3, 2004, pp. 17111716.
8. S. Hartmann, S. Schiefer, S. Scholze, J. Partzsch, C. Mayr, S. Henker, R. Schüffny, Highly integrated packet-based AER communication infrastructure with 3Gevent/s throughput, in: IEEE International Conference on Electronics, Circuits, and Systems ICECS10, 2010, pp. 952955.
9. J. Schemmel, J. Fieres, K. Meier, Wafer-scale integration of analog neural networks, in: IJCNN 2008, 2008, pp. 431438.
10. S. Joshi, S. Deiss, M. Arnold, J. Park, T. Yu, G. Cauwenberghs, Scalable event routing in hierarchical neural array architecture with global synaptic connectivity, in: 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), 2010, pp. 16.
11. M. Lundqvist, M. Rehn, M. Djurfeldt, and A. Lansner Attractor dynamics in a modular network model of neocortex Network: Computation in Neural Systems 17 2006 253 276 (Pubitemid 44898473)
12. E. Izhikevich, J. Gally, and G. Edelman Spike-timing dynamics of neuronal groups Cerebral Cortex 14 2004 933 944 (Pubitemid 38971467)
13. S. Hill, and G. Tononi Modeling sleep and wakefulness in the thalamocortical system Journal of Neurophysiology 93 2005 1671 1698 (Pubitemid 40283749)
14. S. Scholze, S. Henker, J. Partzsch, C. Mayr, R. Schüffny, Optimized queue based communication in VLSI using a weakly ordered binary heap, in: MIXDES 2010, 2010, pp. 316320.
15. X. Jin, S. Furber, J. Woods, Efficient modelling of spiking neural networks on a scalable chip multiprocessor, in: IJCNN 2008, 2008, pp. 28122819.
16. M.A. Dahlem, G. Hiller, A. Panchuk, and E. Schöll Dynamics of delay-coupled excitable neural systems International Journal of Bifurcation and Chaos 19 2009 745 753
17. U. Meyer, J. Shao, S. Chakrabarty, S. Brandt, H. Luksch, and R. Wessel Distributed delays stabilize neural feedback systems Biological Cybernetics 99 2008 79 87
18. D. Knuth The Art of Computer Programming, Sorting and Searching vol. 3 1973 Addison-Wesley MA
19. E. Mumolo, G. Capello, and M. Nolich VHDL design of a scalable VLSI sorting device based on pipelined computation Journal of Computing and Information Technology 12 2004 1 14 (Pubitemid 38767850)
20. K. Ratnayake, A. Amer, An FPGA architecture of stable-sorting on a large data volume: application to video signals, in: Proceedings of the 41st Annual Conference on Information Sciences and Systems, 2007, pp. 431436.
21. C. Thompson The VLSI complexity of sorting IEEE Transactions on Computers C-32 1983 1171 1184
22. K. McLaughlin, S. Sezer, H. Blume, X. Yang, F. Kupzog, and T. Noll A scalable packet sorting circuit for high-speed WFQ packet scheduling IEEE Transactions on VLSI Systems 16 2008 781 791
23. A. Ioannou, and M. Katevenis Pipelined heap (priority queue) management for advanced scheduling in high speed networks IEEE/ACM Transactions on Networking 15 2007 450 461 (Pubitemid 46621622)
24. G. Burton, 16-Channel, DDR LVDS Interface with Per-Channel Alignment, Xilinx, Inc., 1.0 ed., 2006 〈 http://www.xilinx.com/support/documentation/ application-notes/xapp855.pdf 〉.
25. Y. Choi, D.-K. Jeong, W. Kim, J.-B. Lee, C.-H. Kim, An 1.4 Gbps/Ch LVDS receiver with jitter-boundary-based digital de-skew algorithm, in: IEEE Asian Solid-State Circuits Conference, ASSCC 2006, 2006, pp. 383386.
26. M.-D. Ker, C.-H. Wu, Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications, in: Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2006, 2006, p. 4.
27. C.-C. Wang, C.-L. Lee, C.-Y. Hsiao, and J.-F. Huang Clock-and-data recovery design for LVDS transceiver used in LCD panels IEEE Transactions on Circuits and Systems II: Express Briefs 53 2006 1318 1322 (Pubitemid 44824357)
28. K. Shu, and E. Sanchez-Sinencio CMOS PLL Synthesizers: Analysis and Design 2005 Springer
29. A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, and D. Stiurca A low-jitter 1251250 MHz process-independent and ripple-poleless 0.18 μm CMOS PLL based on a sample-reset loop filter IEEE Journal of Solid-State Circuits 36 2001 1673 1683 (Pubitemid 33105931)
30. M. Toyama, S. Dosho, N. Yanagisawa, A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit, in: 2003 Symposium on VLSI Circuits, Digest of Technical Papers, 2003, pp. 185188.
31. S. Williams, H. Thompson, M. Hufford, E. Naviasky, An improved CMOS ring oscillator PLL with less than 4 ps rms accumulated jitter, in: Proceedings of the IEEE Custom Integrated Circuits Conference CICC 2004, pp. 151154.
32. M. Brownlee, P. Hanumolu, K. Mayaram, U.-K. Moon, A 0.5 to 2.5 GHz PLL with fully differential supply-regulated tuning, in: IEEE International Solid-State Circuits Conference, ISSCC 2006, Digest of Technical Papers, 2006, pp. 24122421.
33. W. Yan, and H. Luong A 900 MHz CMOS low-phase-noise voltage controlled ring oscillator IEEE Transactions on Circuits and Systems 48 2001
34. C.S. Vaucher Architectures for RF Frequency Synthesizers 2002 Kluwer Academic Publishers
35. S. Höppner, S. Henker, R. Schüffny, A behavioral PLL model with timing jitter due to white and flicker noise sources, in: Proceedings of GMM/ITG-Fachtagung Analog, 2008, pp. 125130.
36. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ansi/tia/eia-644 ed., 2001.
37. S. Jamasb, R. Jalilizeinali, P. Chau, A 622 MHz stand-alone LVDS driver pad in 0.18 μm CMOS, in: Proceedings of the 44th IEEE Midwest Symposium on Circuits and Systems MWSCAS 2001, vol. 2, 2001, pp. 610613.
38. R. Kleczek, The design of low power 11.6 mW high speed 1.8 Gb/s stand-alone LVDS driver in 0.18 μm CMOS, in: Proceedings of the 17th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES 2010, pp. 337342.
39. A. Tajalli, and Y. Leblebici A slew controlled LVDS output driver circuit in 0.18 μm CMOS technology IEEE Journal of Solid-State Circuits 44 2009 538 548
40. F. Zhang, Z. Yang, W. Feng, H. Cui, L. Huang, W. Hu, A high speed CMOS transmitter and rail-to-rail receiver, in: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, 2008, pp. 6770.
41. J.A. Tierno, A.V. Rylyakov, and D.J. Friedman A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI IEEE Journal of Solid-State Circuits 43 2008 42 51
42. G. Torralba, V. Angelov, V. Gonzalez, V. Lindenstruth, and E. Sanchis A VLSI for deskewing and fault tolerance in LVDS links IEEE Transactions on Nuclear Science 53 2006 801 809 (Pubitemid 44109351)
43. H. Eisenreich, C. Mayr, S. Henker, M. Wickert, and R. Schüffny A novel ADPLL design using successive approximation frequency control Elsevier Microelectronics Journal 40 2009 1613 1622
44. R.J. Baker CMOS Circuit Design Layout and Simulation second ed. 2005 IEEE, Wiley Interscience
45. R. Nonis, E. Palumbo, P. Palestri, and L. Selmi A design methodology for MOS current-mode logic frequency dividers IEEE Transactions on Circuits and Systems I: Regular Papers 54 2007 245 254 (Pubitemid 46444257)
46. J. Maneatis Low-jitter process-independent DLL and PLL based on self-biased techniques IEEE Journal of Solid-State Circuits 31 11 1996
47. S. Höppner, R. Schüffny, M. Nemes, A low-power, robust multi-modulus frequency divider for automotive radio applications, in: MIXDES - 16th International Conference on Mixed Design of Integrated Circuits & Systems, MIXDES09, 2009, pp. 205209.
48. G. Cervelli, A. Marchioro, and P. Moreira A 0.13 μm CMOS serializer for data and trigger optical links in particle physics experiments IEEE Transactions on Nuclear Science 51 2004 1 12
49. C. Zamarreno-Ramos, R. Serrano-Gotarredona, T. Serrano-Gotarredona, B. Linares-Barranco, LVDS interface for AER links with burst mode operation capability, in: IEEE International Symposium on Circuits and Systems, ISCAS 2008, 2008, pp. 644647.
50. M. Giulioni, Networks of Spiking Neurons and Plastic Synapses: Implementation and Control, Ph.D. Thesis, Universita degli studi di Roma Tor Vergata, 2008.