An FPGA architecture of stable-sorting on a large data volume: Application to video signals

Forty-first Annual Conference on Information Sciences and Systems, CISS 2007 - Proceedings

Volumn , Issue , 2007, Pages 431-436

  Ratnayake, Kumara ^a   Amer, Aishy ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

Field programmable gate arrays; Sorting; Video signal processing

Indexed keywords

HARDWARE RESOURCES; SOFTWARE-BASED IMPLEMENTATIONS;

ALGORITHMS; COMPUTER SOFTWARE; MATLAB; MICROPROCESSOR CHIPS; VIDEO SIGNAL PROCESSING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 44049105467     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CISS.2007.4298343     Document Type: Conference Paper

References (10)

1. A. Amer and E. Dubois, "Fast and reliable structure-oriented video noise estimation," IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 1, pp. 113-118, Jan 2005.
2. A.A. Colavita, A. Cicuttin, F. Frantik, and G. Capello, "Ortchip: A vlsi implementation of a hardware algorithm for continuous data sorting," IEEE Journal of Solid State Circuits, vol. 38, pp. 1076-1079, June 2003.
3. K. Ramayake and A. Amer, "An fpga-based implementation of spatio-temporal object segmentation," in Proc. IEEE Int. Conference on Image Processing (IClP), pp. 3265-3260, October 2006.
4. M. Bednara, O. Beyer, J. Teich, and R. Wanka, "Tradeoff analysis and architecture design of a hybrid hardware/software sorter," IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 299-309, July 2000.
5. H.H. Seward, "Information sorting in the application of electronic digital computers to business operations," MS. thesis, Massachusetts Institute of Technology (MIT), 1954.
6. C. Y. Huang, G. J. Yu, and B. D. Liu, "A hardware design approach for merge-sorting network," Proceedings of the 2001 IEEE International Conference on Circuits and Systems, vol. 4, pp. 534-537, May 2001.
7. R. Maheshwari, S.S.S.P. Rao, and P.G. Poonadia, "Fpga implementation of median filter," Proceedings on VLSI Design, pp. 523-524, Jan 1997.
8. S.A. Fahmy, P.Y.K. Cheung, and W. Luk, "Novel fpga-based implementation of median and weighted median filters for image processing," IEEE International Conference on Field Programmable Logic and Applications, pp. 142-147, Aug 2005.
9. MS. Hamid andS. Marshal, "Fpga realisation of the genetic algorithm for the design of gray-scale soft morphological filters," International Conference on Visual Information Engineering, pp. 141- 144, July 2003.
10. K. Benkrid, D. Crookes, and A. Benkrid, "Design and implementation of a novel algorithm for general purpose median filtering on fpgas," International Symposium on Circuits and Systems, vol. 4, pp. 425-428, May 2002.