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Volumn , Issue , 2010, Pages 950-953

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput

Author keywords

Configuration over AER; FPGA event routing; Gigaevent serial AER; Packet based AER

Indexed keywords

ASYNCHRONOUS TRANSMISSION; BAND-WIDTH UTILIZATION; COMMUNICATION BANDWIDTH; COMMUNICATION INFRASTRUCTURE; CONFIGURATION OVER AER; EVENT ROUTING; FPGA DESIGN; GIGAEVENT SERIAL AER; HIGHLY INTEGRATED; MECHANICAL INTEGRATION; NEURAL COMMUNICATION; NEUROMORPHIC SYSTEMS; NEUROMORPHIC VLSI; PACKET-BASED; PACKET-BASED AER; TRANSMISSION RATES; TRANSMISSION SPEED; WAFER-SCALE;

EID: 79953121351     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2010.5724670     Document Type: Conference Paper
Times cited : (22)

References (8)
  • 1
    • 70349253937 scopus 로고    scopus 로고
    • CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking
    • R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, and R. et al. Paz-Vicente, "CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking," IEEE Transactions on Neural Networks, vol. 20, no. 9, pp. 1417-1434, 2009.
    • (2009) IEEE Transactions on Neural Networks , vol.20 , Issue.9 , pp. 1417-1434
    • Serrano-Gotarredona, R.1    Oster, M.2    Lichtsteiner, P.3    Linares-Barranco, A.4    Paz-Vicente, R.5
  • 2
    • 51749084209 scopus 로고    scopus 로고
    • A serial communication infrastructure for multi-chip address event systems
    • D.B. Fasnacht, A.M. Whatley, and G. Indiveri, "A serial communication infrastructure for multi-chip address event systems," in ISCAS 2008, 2008, pp. 648-651.
    • (2008) ISCAS 2008 , pp. 648-651
    • Fasnacht, D.B.1    Whatley, A.M.2    Indiveri, G.3
  • 3
    • 34548824399 scopus 로고    scopus 로고
    • High-speed serial AER on FPGA
    • H.K.O. Berge and P. Häfliger, "High-speed serial AER on FPGA," in ISCAS 2007, 2007, pp. 857-860.
    • (2007) ISCAS 2007 , pp. 857-860
    • Berge, H.K.O.1    Häfliger, P.2
  • 4
    • 77955993002 scopus 로고    scopus 로고
    • A wafer-scale neuromorphic hardware system for large-scale neural modeling
    • J. Schemmel, D. Brüderle, A. Grübl, M. Hock, K. Meier, and S. Millner, "A wafer-scale neuromorphic hardware system for large-scale neural modeling," in ISCAS 2010, 2010, pp. 1947-1950.
    • (2010) ISCAS 2010 , pp. 1947-1950
    • Schemmel, J.1    Brüderle, D.2    Grübl, A.3    Hock, M.4    Meier, K.5    Millner, S.6
  • 6
    • 56349166622 scopus 로고    scopus 로고
    • Wafer-scale integration of analog neural networks
    • J. Schemmel, J. Fieres, and K. Meier, "Wafer-scale integration of analog neural networks," in IJCNN 2008, 2008, pp. 431-438.
    • (2008) IJCNN 2008 , pp. 431-438
    • Schemmel, J.1    Fieres, J.2    Meier, K.3
  • 8
    • 56349126464 scopus 로고    scopus 로고
    • Efficient modelling of spiking neural networks on a scalable chip multiprocessor
    • X. Jin, S.B. Furber, and J.V. Woods, "Efficient modelling of spiking neural networks on a scalable chip multiprocessor," in IJCNN 2008, 2008, pp. 2812-2819.
    • (2008) IJCNN 2008 , pp. 2812-2819
    • Jin, X.1    Furber, S.B.2    Woods, J.V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.