A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1673-1683

  Maxim, Adrian ^a,b   Scott, Baker ^a,c   Schneider, Edmund M ^a,d   Hagge, Melvin L ^a,d   Chacko, Steven ^d   Stiurca, Dan ^a,d  

^a IEEE   (United States)

^b MAXIM INTEGRATED PRODUCTS   (United States)

^c Channel Technology   (United States)

^d Cirrus Logic   (United States)

Author keywords

CMOS; Frequency synthesizer; Jitter; Oscillator; Phase locked loop; Sample reset loop filter

Indexed keywords

BANDGAP VOLTAGE; FEEDFORWARD ZERO; RIPPLE-FREE CONTROL SIGNAL; RIPPLE-POLELESS; SAMPLE-RESET LOOP FILTER;

CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FREQUENCY SYNTHESIZERS; JITTER; MATHEMATICAL MODELS; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC);

PHASE LOCKED LOOPS;

EID: 0035506811     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962287     Document Type: Article

References (9)

1. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
2. Low-jitter process-independent DLL and PLL based on self-biased techniques
3. Cell-based fully integrated CMOS frequency synthesizer
4. Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and 50 ps jitter
5. A low noise fast-lock phase-locked loop with adaptive bandwidth control
6. A 1.4 GHz differential low noise CMOS frequency synthesizer using a wideband PLL architecture
7. Design of high performance CMOS charge-pumps in phase locked loops
8. A low-jitter 125-1250 MHz process-independent 0.18-μm CMOS PLL based on a sample-reset loop filter
9. A novel physical based model of deep-submicron CMOS transistors mismatch for monte carlo SPICE simulation