메뉴 건너뛰기




Volumn , Issue , 2007, Pages 857-860

High-speed serial AER on FPGA

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERFACES (MATERIALS); PRINTED CIRCUIT BOARDS;

EID: 34548824399     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378041     Document Type: Conference Paper
Times cited : (32)

References (10)
  • 3
    • 0001326828 scopus 로고
    • A communication scheme for analog VLSI perceptive systems
    • June
    • A. Mortara, E. Vittoz, and P. Venier, "A communication scheme for analog VLSI perceptive systems," IEEE Journal of Solid-State Circuits, vol. 30, no. 6, pp. 660-669, June 1995.
    • (1995) IEEE Journal of Solid-State Circuits , vol.30 , Issue.6 , pp. 660-669
    • Mortara, A.1    Vittoz, E.2    Venier, P.3
  • 8
    • 0020812712 scopus 로고
    • A DC-balanced, partitioned-block, 8b/10b transmission code
    • A. Widmer and P. Franaszek, "A DC-balanced, partitioned-block, 8b/10b transmission code," IBM J. RES. DEVELOP, vol. 27, no. 5, 1983.
    • (1983) IBM J. RES. DEVELOP , vol.27 , Issue.5
    • Widmer, A.1    Franaszek, P.2
  • 10
    • 4043065121 scopus 로고    scopus 로고
    • A burst-mode word-serial address-event link III: Analysis and test results
    • July
    • K. Boahen, "A burst-mode word-serial address-event link III: Analysis and test results," IEEE Transactions on Circuits and Systems I, vol. 51, no. 7, pp. 1292-1300, July 2004.
    • (2004) IEEE Transactions on Circuits and Systems I , vol.51 , Issue.7 , pp. 1292-1300
    • Boahen, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.