CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking

IEEE Transactions on Neural Networks

Volumn 20, Issue 9, 2009, Pages 1417-1438

  Serrano Gotarredona, Rafael ^a,b   Oster, Matthias ^c,d   Lichtsteiner, Patrick ^c,e   Linares Barranco, Alejandro ^f   Paz Vicente, Rafael ^f   Gómez Rodríguez, Francisco ^f   Camunas Mesa, Luis ^a   Berner, Raphael ^c   Rivas Perez, Manuel ^f   Delbrück, Tobi ^c   Liu, Shih Chii ^c   Douglas, Rodney ^c   Hafliger, Philipp ^g   Jimenez Moreno, Gabriel ^f   Civit Ballcels, Anton ^f   Serrano Gotarredona, Teresa ^a   Acosta Jimenez, Antonio J ^a   Linares Barranco, Bernabé ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^b Department of Austriamicrosystems ^*  (Spain)

^c Institute of Neuroinformatics Zurich   (Switzerland)

^d VARIAN MEDICAL SYSTEMS   (Switzerland)

^e ESPROS Photonics   (Switzerland)

^f UNIVERSITY OF SEVILLE   (Spain)

^g UNIVERSITY OF OSLO   (Norway)

Author keywords

Address event representation (AER); Neuromorphic chips; Neuromorphic systems; Vision

Indexed keywords

ADDRESS-EVENT REPRESENTATION; ADDRESS-EVENT REPRESENTATION (AER); COMMUNICATION FRAMEWORK; EUROPEAN UNION; HIGH-SPEED; MIXED SIGNAL; NERVOUS SYSTEM; NEUROMORPHIC CHIPS; NEUROMORPHIC SYSTEMS; PARALLEL HARDWARE; SPIKING CELLS; VISUAL OBJECT RECOGNITION;

HARDWARE; OBJECT RECOGNITION;

BIOCHIPS;

ACTION POTENTIAL; ARTICLE; ARTIFICIAL INTELLIGENCE; ARTIFICIAL NEURAL NETWORK; COMPUTER; HUMAN; LEARNING; MOVEMENT PERCEPTION; NERVE CELL; PATTERN RECOGNITION; PHYSIOLOGY; PSYCHOMOTOR PERFORMANCE; RETINA; SYNAPSE; TIME; VISION;

ACTION POTENTIALS; ARTIFICIAL INTELLIGENCE; COMPUTERS; HUMANS; LEARNING; MOTION PERCEPTION; NEURAL NETWORKS (COMPUTER); NEURONS; PATTERN RECOGNITION, VISUAL; PSYCHOMOTOR PERFORMANCE; RETINA; SYNAPSES; TIME FACTORS; VISION, OCULAR; VISUAL PERCEPTION;

EID: 70349253937     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2009.2023653     Document Type: Article

References (95)

1. T. Serre, "Learning a dictionary of shape-components in visual cortex: Comparison with neurons, humans and machines," MIT. Comput. Sci. & AI Lab, Cambridge, MA, Tech. Rep. MIT-CSAIL-TR-2006-028 CBCL-260, 2006.
2. S. Thorpe, D. Fize, and C. Marlot, "Speed of processing in the human visual system," Nature, vol. 381, pp. 520-522, Jun. 1996.
3. S. Lawrence, C. L. Giles, A. Tsoi, and A. Back, "Face recognition: A convolutional neural network approach," IEEE Trans. Neural Netw., vol. 8, no. 1, pp. 98-113, Jan. 1997.
4. Y. Le Cun and Y. Bengio, "Convolutional networks for images, speech, and time series," in Handbook of Brain Theory and Neural Networks M. A. Arbib, Ed. Cambridge, MA: MIT Press, 1995, pp. 255-258.
5. M. Matsugu, K. Mori, M. Ishi, and Y. Mitarai, "Convolutional spiking neural network model for robust face detection," in roc. 9th Int. Conf. Neural Inf. Process., 2002, vol. 2, pp. 660-664.
6. B. Fasel, "Robust face analysis using convolutional neural networks," in Proc. Int. Conf. Pattern Recognit., 2002, pp. 40-43.
7. M. Browne and S. S. Ghidary, "Convolutional neural networks for image processing: An application in robot vision," in Advances in Artificial Intelligence. Cambridge, MA: MIT Press, 2003, pp. 641-652.
8. C. Neubauer, "Evaluation of convolution neural networks for visual recognition," IEEE Trans. Neural Netw., vol. 9, no. 4, pp. 685-696, Jul. 1998.
9. K. Fukushima, "Analysis of the process of visual pattern recognition by the neocognitron," Neural Netw., vol. 2, pp. 413-420, 1989.
10. L. Itti, "Quantitative modeling of perceptual salience at human eye position," Vis. Cogn., vol. 14, no. 4, pp. 959-984, 2006.
11. L. Itti, "Quantifying the contribution of low-level saliency to human eye movements in dynamic scenes," Vis. Cogn., vol. 12, no. 6, pp. 1093-1123, Aug. 2005.
12. H. Fujii, H. Ito, K. Aihara, N. Ichinose, and M. Tsukada, "Dynamical cell assembly hypothesis - Theoretical possibility of spatio-temporal coding in the cortex," Neural Netw., vol. 9, pp. 1303-1350, 1996.
13. G. M. Shepherd, The Synaptic Organization of the Brain, 3rd ed. Oxford, U.K.: Oxford Univ. Press, 1990.
14. T. Crimmins, "Geometric filter for speckle reduction," Appl. Opt. vol. 24, pp. 1438-1443, 1985.
15. S. Grossberg, E. Mingolla, and J.Williamson, "Synthetic aperture radar processing by a multiple scale neural system for boundary and surface representation," Neural Netw., vol. 8, no. 7/8, pp. 1005-1028, 1995.
16. S. Grossberg, E. Mingolla, and W. D. Ross, "Visual brain and visual perception: Howdoes the cortex do perceptual grouping?," Trends Neurosci., vol. 20, pp. 106-111, 1997.
17. E. Mingolla, W. Ross, and S. Grossberg, "A neural network for enhancing boundaries and surfaces in synthetic aperture radar images," Neural Netw., vol. 12, no. 3, pp. 499-511, 1999.
18. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, and B. Linares-Barranco, "A neuromorphic cortical-layer microchip for spike- based event processing vision systems," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2548-2566, Dec. 2006.
19. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128 × 128 120 dB 30 mW asynchronous vision sensor that responds to relative intensity change," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2006, pp. 508-509.
20. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128 × 128 120 dB 15 μs latency asynchronous temporal contrast vision sensor," IEEE J. Solid State Circuits, vol. 43, no. 2, pp. 566-576, Feb. 2007.
21. T. Delbruck and P. Lichtsteiner, "Fully programmable bias current generator with 24 bit resolution per bias," in Proc. IEEE Int. Symp. Circuits Syst., Athens, Greece, 2006, pp. 2849-2852.
22. T. Delbrück, jAER Open Source Project, [Online]. Available: http:// jaer.wiki.sourceforge.net
23. J. Costas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona, and B. Linares-Barranco, "A contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 7, pp. 1444-1458, Jul. 2007.
24. M. Sivilotti, "Wiring considerations in analog VLSI systems with application to field-programmable networks," Ph.D. dissertation, Comput. Sci. Div., California Inst. Technol., Pasadena, CA, 1991.
25. M. Mahowald, "VLSI analogs of neural visual processing: A synthesis of form and function," Ph.D. dissertation, Comput. Sci. Div., California Inst. Technol., Pasadena, CA, 1992.
26. M. Mahowald, An Analog VLSI Stereoscopic Vision System. Norwell, MA: Kluwer, 1994.
27. J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Silvilotti, and D. Gillespie, "Silicon auditory processors as computer peripherals," IEEE Trans. Neural Netw., vol. 4, no. 3, pp. 523-528, May 1993.
28. J. P. Lazzaro and J. Wawrzynek, "A multi-sender asynchronous extension to the address-event protocol," in Proc. 16th Conf. Adv. Res. VLSI W. J. Dally, J. W. Poulton, and A. T. Ishii, Eds., 1995, pp. 158-169.
29. A. Mortara and E. A. Vittoz, "A communication architecture tailored for analog VLSI artificial neural networks: Intrinsic performance and limitations," IEEE Trans. Neural Netw., vol. 5, no. 3, pp. 459-466, May 1994.
30. A. Mortara, E. A. Vittoz, and P. Venier, "A communication scheme for analog VLSI perceptive systems," IEEE J. Solid-State Circuits, vol. 30, no. 6, pp. 660-669, Jun. 1995.
31. Z. Kalayjian and A. G. Andreou, "Asynchronous communication of 2D motion information using winner-takes-all arbitration," Int. J. Anal. Integr. Circuits Signal Process., vol. 13, no. 1-2, pp. 103-109, Mar./Apr. 1997.
32. K. A. Boahen, "Communicating neuronal ensembles between Neuromorphic Chips," in Neuromorphic Systems Engineering: Neural Networks in Silicon, T. S. Lande, Ed. Norwell, MA: Kluwer, 1998, ch. 11.
33. K. Boahen, "Point-to-point connectivity between neuromorphic chips using address events," IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process., vol. 47, no. 5, pp. 416-434, May 2000.
34. K. A. Boahen, "A burst-mode word-serial address-event link-I: Transmitter design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1269-1280, Jul. 2004.
35. K. A. Boahen, "A burst-mode word-serial address-event Link-II: Receiver design," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1281-1291, Jul. 2004.
36. K. A. Boahen, "A burst-mode word-serial address-event Link-III: Analysis and test results," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1292-1300, Jul. 2004.
37. K. Boahen, ChipGen Silicon Compiler, [Online]. Available: http:// www.stanford.edu/group/brainsinsilicon/Downloads.htm
38. E. Culurciello, R. Etienne-Cummings, and K. A. Boahen, "A biomorphic digital image sensor," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 281-294, Feb. 2003.
39. U. Mallik, M. Clapp, E. Choi, G. Cauwenberghs, and R. Etienne-Cummings, "Temporal change threshold detection imager," in Dig. Tech. Papers IEEE ISSCC, San Francisco, CA, 2005, pp. 362-363.
40. P. F. Ruedi, P. Heim, F. Kaess, E. Grenet, F. Heitger, P. Y. Burgi, S. Gyver, and P. Nussbaum, "A 128 × 128, pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction," IEEE J. Solid- State Circuits, vol. 38, no. 12, pp. 2325-2333, Dec. 2003.
41. C. Shoushun and A. Bermak, "A low power CMOS imager based on time- to-first-spike encoding and fair AER," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 5306-5309.
42. X. G. Qi and J. Harris, "A time-to-first-spike CMOS imager," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, BC, Canada, 2004, pp. 824-827.
43. M. Azadmehr, J. Abrahamsen, and P. Häfliger, "A foveated AER imager chip," in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005, vol. 3, pp. 2751-2754.
44. R. J. Vogelstein, U. Mallik, E. Culurciello, R. Etienne-Cummings, and G. Cauwenberghs, "Spatial acuity modulation of an address-event imager," in Proc. 11th IEEE Int. Conf. Electron. Circuits Syst., Dec. 2004, pp. 207-210.
45. K. A. Zaghloul and K. Boahen, "Optic nerve signals in a neuromorphic chip: Part I and II," IEEE Trans. Biomed. Eng., vol. 51, no. 4, pp. 657-675, Apr. 2004.
46. M. Arias-Estrada, D. Poussart, and M. Tremblay, "Motion vision sensor architecture with asynchronous self-signaling pixels," in Proc. 7th Int. Workshop Comput. Architecture Mach. Perception, 1997, pp. 75-83.
47. C. M. Higgins and S. A. Shams, "A biologically inspired modular VLSI system for visual measurement of self-motion," IEEE Sensors J., vol. 2, no. 6, pp. 508-528, Dec. 2002.
48. E. Özalevli and C. M. Higgins, "Reconfigurable biologically inspired visual motion system using modular neuromorphic VLSI chips," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 79-92, Jan. 2005.
49. G. Indiveri, A. M. Whatley, and J. Kramer, "A reconfigurable neuromorphic VLSI multi-chip system applied to visual motion computation," in Proc. Int. Conf. Microelectron. Neural Fuzzy Bio-Inspired Syst., Granada, Spain, 1999, pp. 37-44.
50. K. Boahen, "Retinomorphic chips that see quadruple images," in Proc. Int. Conf. Microelectron. Neural Fuzzy Bio-Inspired Syst., Granada, Spain, 1999, pp. 12-20.
51. R. Z. Shi and T. K. Horiuchi, "A VLSI model of the bat dorsal nucleus of the Lateral Lemniscus for azimuthal echolocation," in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, 2005, pp. 4217-4220.
52. V. Chan, S.-C. Liu, and A. van Schaik, "AER EAR: A matched silicon cochlea pair with address event representation interface," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 1, pp. 48-59, Jan. 2007.
53. G. Cauwenberghs, N. Kumar, W. Himmelbauer, and A. G. Andreou, "An analog VLSI chip with asynchronous interface for auditory feature extraction," IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process., vol. 45, no. 5, pp. 600-606, May 1998.
54. M. Oster and S.-C. Liu, "Spiking inputs to a spiking winner-take-all circuit," in Advances in Neural Information Processing Systems, Y. Weiss, B. Schölkopf, and J. Platt, Eds. Cambridge, MA: MIT Press, 2006, vol. 18, pp. 1051-1058.
55. J. Abrahamsen, P. Häfliger, and T. S. Lande, "A time domain winner-take-all network of integrate-and-fire neurons," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, BC, Canada, May 2004, vol. V, pp. 361-364.
56. E. Chicca, G. Indiveri, and R. J. Douglas, "An event-based VLSI network of integrate-and-fire neurons," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, BC, Canada, 2004, vol. V, pp. 357-360.
57. T. Teixeira, A. G. Andreou, and E. Culurciello, "Event-based imaging with active illumination in sensor networks," in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, 2005, pp. 644-647.
58. P. Vernier, A. Mortara, X. Arreguit, and E. A. Vittoz, "An integrated cortical layer for orientation enhancement," IEEE J. Solid-State Cicuits, vol. 32, no. 2, pp. 177-186, Feb. 1997.
59. T. Y. W. Choi, B. E. Shi, and K. Boahen, "An ON-OFF orientation selective address event representation image transceiver chip," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 342-353, Feb. 2004.
60. T. Serrano-Gotarredona, A. G. Andreou, and B. Linares-Barranco, "AER image filtering architecture for vision processing systems," IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process., vol. 46, no. 9, pp. 1064-1071, Sep. 1999.
61. A. Jiménez-Fernández, C. D. Luján, A. Linares-Barranco, F. G.-. Rodríguez, M. Rivas, G. Jiménez, and A. Civit, "Address-event based platform for bio-inspired spiking systems," Proc. SPIE, vol. 6592, 2007, DOI: 10.1117/12.724156, 659206.
62. R. Paz, A. Linares-Barranco, M. Rivas, L. Miró, S. Vicente, G. Jiménez, and A. Civit, "AER tools for communications and debugging," in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 3253-3256.
63. E. Chicca, A. M. Whatley, V. Dante, P. Lichtsteiner, T. Delbrück, P. D. Giudice, R. J. Douglas, and G. Indiveri, "A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity," IEEE Trans. Circuits Syst. I, Reg. Papers vol. 54, no. 5, pp. 981-993, May 2007.
64. R. Berner, T. Delbruck, A. Civit-Balcells, and A. Linares-Barranco, "A 5 Meps $100 USB2.0 address-event monitor-sequencer interface," in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 2451-2454.
65. C. Kimme, D. H. Ballard, and J. Slansky, "Finding circles by an array of accumulators," Commun. Assoc. Comput. Mach., vol. 18, pp. 120-122, 1975.
66. M. Oster, Y. Wang, R. Douglas, and S.-C. Liu, "Quantification of a spike- based winner-take-all VLSI network," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 10, pp. 3160-3169, Nov. 2008.
67. M. Oster and S.-C. Liu, "Quantifying input and output statistics of a winner-take-all network in a vision system," in Proc. IEEE Int. Symp. Circuits Syst., New Orleans, LA, May 2007, pp. 853-856.
68. S.-C. Liu and M. Oster, "Feature competition in a spike-based winner-take-all VLSI network," in Proc. IEEE Int. Symp. Circuits Syst., Island of Kos, Greece, May 2006, pp. 3634-3637.
69. M. Oster and S. Liu, "Spiking inputs to a winner-take-all network," in Advances in Neural Information Processing Systems (NIPS), Y.Weiss, B. Schölkopf, and J. Platt, Eds. Cambridge, MA: MIT Press, 2005, vol. 18, pp. 1051-1058.
70. M. Oster, R. Douglas, and S.-C. Liu, "Computation with spikes in a winner-take-all network," in Neural Computation. Cambridge, MA: MIT Press, to be published.
71. M. Boegerhausen, P. Suter, and S.-C. Liu, "Modeling short-term synaptic depression in silicon," Neural Comput., vol. 15, pp. 331-348, 2003.
72. C. Mead and T. Delbrück, "Scanners for visualizing activity of analog VLSI circuitry," Int. J. Anal. VLSI Signal Process., vol. 1, pp. 93-106, 1991.
73. P. Häfliger, "Adaptive WTA with an analog VLSI neuromorphic learning chip," IEEE Trans. Neural Netw., vol. 18, no. 2, pp. 551-572, Mar. 2007.
74. R. Kempter, W. Gerstner, and J. L. van Hemmen, "Spike-based compared to rate-based Hebbian learning," Neural Inf. Process. Syst., vol. 11, pp. 125-131, 1999.
75. P. Häfliger and H. K. Riis, "A multi-level static memory cell," in Proc. IEEE Int. Symp. Circuits Syst., Bangkok, Thailand, May 2003, vol. 1, pp. 22-25.
76. E. Oja, "A simplified neuron model as principal component analyzer," J. Math. Biol., vol. 15, pp. 267-273, 1982.
77. T. D. Sanger, "Optimal unsupervised learning in a single-layer linear feedforward neural network," Neural Netw., vol. 2, pp. 459-473, 1989.
78. L. A. Akers, D. K. Ferry, and R. O. Grondin, "Synthetic neural systems in the 1990s," in An Introduction to Neural and Electronic Networks S. F. Zornetzer, J. L. Davis, C. Lau, and McKenna, Eds. New York: Academic, 1995, pp. 359-387.
79. E. Brown, R. Barbieri, V. Ventura, R. Kass, and L. Frank, "The time-rescaling theorem and its application to neural spike train data analysis," Neural Comput., vol. 14, no. 2, pp. 325-346, 2002.
80. A. Linares-Barranco, G. Jimenez-Moreno, B. Linares-Barranco, and A. Civit-Ballcels, "On algorithmic rate-coded AER generation," IEEE Trans. Neural Netw., vol. 17, no. 3, pp. 771-788, May 2006.
81. A. Delorme, J. Gautrais, and S. Thorpe, "SpikeNET: A simulator for modeling large networks of integrate-and-fire neurons," Neurocomputing, vol. 26-27, pp. 989-96, 1999.
82. A. Delorme, L. Perrinet, and S. Thorpe, "Networks of integrate-and-fire neurons using rank order Coding B: Spike timing dependent plasticity and emergence of orientation selectivity," Neurocomputing, vol. 38-40, pp. 539-45, 2001.
83. D. George and F. T. Sommer, "Computing with inter-spike interval codes in networks of integrate and fire neurons," Neurocomputing, vol. 65-66, pp. 415-420, 2005.
84. F. Gomez-Rodriguez, R. Paz, L. Miró, A. Linares-Barranco, G. Jiménez, and A. Civit, "Two hardware implementations of the exhaustive synthetic AER generation method," in Lecture Notes in Computer Science. Berlin, Germany: Springer-Verlag, 2005, vol. 3512, pp. 534-540.
85. A. Linares-Barranco, M. Oster, D. Cascado, G. Jiménez, A. Civit, and B. Linares-Barranco, "Inter-spikes-intervals analysis of AER Poisson-like generator hardware," Neurocomputing, vol. 70, no. 16-18, pp. 2692-2700, 2007.
86. L. Camuñas-Mesa, A. Acosta-Jiménez, T. Serrano-Gotarredona, and B. Linares-Barranco, "Fully digital AER convolution chip for vision processing," in Proc. IEEE Int. Symp. Circuits Syst., Seattle,WA, May 2008, pp. 652-655.
87. T. Delbruck and P. Lichtsteiner, "Fast sensory motor control based on event-based hybrid neuromorphic-procedural system," in Proc. IEEE Int. Symp. Circuits Syst., New Orleans, LA, 2007, pp. 845-848.
88. H. Garn and M. Krenn, Smart Eye TDS-Traffic Data Sensor, [Online]. Available: http://www.smart-systems.at/products/ products_smart_optical_sensors_t_en.html
89. J. A. Perez-Carrasco, T. Serrano-Gotarredona, C. Serrano-Gotarredona, B. Acha, and B. Linares-Barranco, "High-speed character recognition system based on a complex hierarchical AER architecture," in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 2150-2153.
90. T. Delbruck, "Frame-free dynamic digital vision," in Proc. Int. Symp. Secure-Life Electron. Adv. Electron. Quality Life Soc., Tokyo, Japan, 2008, pp. 21-26.
91. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J. A. Perez-Carrasco, A. Linares-Barranco, G. Jimenez-Moreno, A. Civit-Ballcels, and B. Linares-Barranco, "On reald time AER 2D convolutions hardware for neuromorphic spike based cortical processing," IEEE Trans. Neural Netw., vol. 19, no. 7, pp. 1196-1219, Jul. 2008.
92. TMS320DM6446 Digital Media System-on-Chip (DMSoC) Datasheet, Texas Instruments,, Houston, TX, SPRS283E-December 2005-Revised March 2007.
93. TMS320DM355 Digital Media System-on-Chip (DMSoC) Datasheet, Texas Instruments, Houston, TX, SPRS463-September 2007.
94. T. Kohonen, Self-Organization and Associative Memory, 3rd ed. New York: Springer-Verlag, 1989.
95. B. Cope, P. Y. K. Cheung, W. Luk, and S. Witt, "Have GPUs made FPGAs redundant in the field of Video Processing?," in Proc. Int. Conf. Field Programmable Technol., 2005, pp. 111-118.