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Volumn , Issue , 2008, Pages 644-647

LVDS interface for AER links with burst mode operation capability

Author keywords

[No Author keywords available]

Indexed keywords

BANDPASS FILTERS; CABLES; COMPUTER NETWORKS; TECHNICAL PRESENTATIONS; TRANSMITTERS;

EID: 51749088349     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541500     Document Type: Conference Paper
Times cited : (6)

References (8)
  • 1
    • 51749093155 scopus 로고
    • Wiring considerations in analog VLSI systems with applications to field programmable networks. Ph. D. Thesis, California Institute of Technology, Pasadena, CA
    • M.S. Silvilotti, Wiring considerations in analog VLSI systems with applications to field programmable networks. Ph. D. Thesis, California Institute of Technology, Pasadena, CA, 1991.
    • (1991)
    • Silvilotti, M.S.1
  • 2
    • 84864053572 scopus 로고    scopus 로고
    • AER Building Blocks for Multi-Layer Multi-Chips Neuromorphic Vision Systems. Advances in Neural Information Processing Systems
    • R. Serrano-Gotarredona et al, AER Building Blocks for Multi-Layer Multi-Chips Neuromorphic Vision Systems. Advances in Neural Information Processing Systems, NIPS'06, vol.18, pp. 1217-1224.
    • NIPS'06 , vol.18 , pp. 1217-1224
    • Serrano-Gotarredona, R.1
  • 3
    • 4043137376 scopus 로고    scopus 로고
    • A burst-mode word-serial address-event link-I, II and III
    • July
    • K. A. Boahen, A burst-mode word-serial address-event link-I, II and III. IEEE Transactions on Circuits and Systems I, vol. 51, num. 7, pp. 1269-1300, July, 2004.
    • (2004) IEEE Transactions on Circuits and Systems I , vol.51 , Issue.7 , pp. 1269-1300
    • Boahen, K.A.1
  • 4
    • 51749114932 scopus 로고    scopus 로고
    • ANSI/TEIA/EIA-644-1995, Electrical Characteristics of Low Voltage Differential Signalling (LVDS) Interface Circuits. Telecommunications Industry Association, Nov. 15, 1995.
    • ANSI/TEIA/EIA-644-1995, Electrical Characteristics of Low Voltage Differential Signalling (LVDS) Interface Circuits. Telecommunications Industry Association, Nov. 15, 1995.
  • 6
    • 0035309966 scopus 로고    scopus 로고
    • LVDS I/O Interface for Gp/s-per-pin Operation in 0.35 μm CMOS
    • April
    • A. Boni, A. Pierazzi, D. Vecchi, LVDS I/O Interface for Gp/s-per-pin Operation in 0.35 μm CMOS. IEEE Journal of Solid-State Circuits, vol. 36, No. 4, pp. 706-711, April, 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.4 , pp. 706-711
    • Boni, A.1    Pierazzi, A.2    Vecchi, D.3
  • 8
    • 25144466873 scopus 로고    scopus 로고
    • A.L. Coban, M.H. Korogolu, K.A. Ahmed, A 2.5-3.125 Gbps Quad Transceiver with Second-Order Analog DLL-Based CDRs. IEEE Journal of Solid State Circuits, 40, No.9, pp. 1940-1947, September 2005.
    • A.L. Coban, M.H. Korogolu, K.A. Ahmed, A 2.5-3.125 Gbps Quad Transceiver with Second-Order Analog DLL-Based CDRs. IEEE Journal of Solid State Circuits, vol. 40, No.9, pp. 1940-1947, September 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.