VHDL design of a scalable VLSI sorting device based on pipelined computation

Journal of Computing and Information Technology

Volumn 12, Issue 1, 2004, Pages 1-14

  Mumolo, Enzo ^a   Capello, Gabriele ^b   Nolich, Massimiliano ^a  

^a UNIVERSITY OF TRIESTE   (Italy)

^b Neonseven   (Italy)

Author keywords

Pipeline computation; Scalability; Sorting algorithms; VHDL language; VLSI algorithms

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; INTEGRATED CIRCUIT DESIGN; PIPELINES; PRODUCT DESIGN; SCALABILITY; VLSI CIRCUITS;

BUILDING BLOCKES; PIPELINED COMPUTATION; PROPOSED ARCHITECTURES; SORTING ALGORITHM; SORTING DEVICE; STRUCTURAL SYNTHESIS; TIME PARAMETER; VHDL LANGUAGE;

SORTING;

EID: 75549091551     PISSN: 13301136     EISSN: 18463908     Source Type: Journal    
DOI: 10.2498/cit.2004.01.01     Document Type: Article

References (29)

1. B. AHN AND J. M. MURRAY, A pipeline, expandible sorting engine implemented in CMOS technology, in IEEE Int. Symposium on Circuits and Systems, ISCAS89, 1989, pp. 134-137
2. G. ALEXIOU AND D. STILIADIS, Design and implementation of a highperformance, modular sorting engine, in IEEE European Design and Test Conference, 1994, pp. 2-8
3. Alliance, http://www.asim.lip6.fr/alliance
4. K. E. BATCHER, Sorting Networks and their Applications, in Proc. AFIPS Spring Joint Comput. Conf., Vol. 32, 1968
5. A. BELLETTINI, A. FERRARI, R.GUERRIERI, AND G. BACCARANI, A digital parallel VLSI architecture for fuzzy database mining, in IEEEWorld Congress on Computational Intelligence, 1994
6. G. M. BLAIR, Low Cost Sorting Circuit for VLSI, IEEE Trans. on Circuits and Systems, 1996
7. V. BRAJOVIC AND T. KANADE, A VLSI sorting image sensor: global massively parallel intensityto-time processing for low-latency adaptive vision, IEEE Trans. on robotics and automation, 1999, pp. 67-75
8. C. CHAKRABARTI, Sorting Network Based Architectures for Median Filters, IEEE Trans. on Circuits and Systems-II, 40, 1993
9. T. C. CHAN, K. P. ESWAREN, V. Y. LUM, AND C. TUNG, Simplified Odd-even Sort Using Multiple Shift-Register Loops, Int. J. Comput. Inform. Sci., 7, 1978
10. T. CORMEN, C. LEISERSON, AND L. RIVEST, Introduction to Algorithms, The MIT Press, 1990
11. S. B. GU LIN, A expansibile current-mode sorting integrated circuit for pattern recognition, in Int. Joint Conference on Neural Network, vol. 5, 1999, pp. 3123-3127
12. J. JA'JA AND R. M. OWENS, VLSI Sorting with Reduced Hardware, IEEE trans. on Computers, vol. C-33, 1984
13. M. KARAMAN, L.ONURAL, AND A. ATALAR, A general purpose VLSI median filter and its application for image processing, in Melecon 89, 1989, pp. 366-369
14. D. E. KNUTH, The Art of Computer Programming, Sorting and Searching, AddisonWesley, 1975
15. M. KUMAR AND D. D. HIRSHBERG, An Efficient Implementation of Batcher's Odd-even Merge Algorithm and its Application in Parallel Sorting Schemes, IEEE Trans. on Computers, vol. C-32, 1983
16. J.-D. LEE AND K. E. BATCHER, Minimizing Communication in the Bitonic Sort, IEEE Transaction on Parallel and Distributed Systems, 2000
17. C.-S. LIN AND B.-D. LIU, Design of pipelined and expandable sorting architecture with simple control scheme, in IEEE International Symposium on Circuits and Systems ISCAS 2002, 2002
18. E. E. LINDERSTROM AND J. S. VITTER, The design and analysis of bucket sort for bubble memory secondary storage, IEEE Trans. on Computers, vol. C-32, 1985, pp. 218-233
19. Magic, http:bwrc.eecs.berkley.edu/Classes/IcBook/magic/index.html
20. G. M.MEGSON, Sorting without exchanges on a bitserial systolic array, IEE Proceedings, 137, 1990, pp. 345-352
21. G. MIRANKER, L. TANG, AND C. K. WONG, A zerotime VLSI sorter, IBM J. Res. Develop., 27, 1983, pp. 140-148
22. D. NASSIMI AND S. SAHNI, Bitonic Sort on a Mesh-Connected Parallel Computer, IEEE Trans. on Computers, vol. C-28, 1979
23. S. OLARIU, M. C. PINOTTI, AND S. Q. ZHENG, An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device, IEEE Transaction on Computers, 2000
24. I. PITAS AND A. N. VENETSANOPULOS, Non Linear Digital Filters, Kluwer Academic Publishers, 1990
25. D. S. K. POK, C. I. H. CHEN, J. J. SCHAMUS, C. T. MONTGOMERY, AND J. B. Y. TSUI, Chip design for monobit receiver, IEEE Trans. on Microwave Theory and Techniques, 45, 1997, pp. 2283-2295
26. D. C. STEPHENS, J. C. R. BENNET, AND H. YHANG, Implementing scheduling algorithms in high speed networks, IEEE Journal on Selected Areas in Communications, 1999
27. C. D. THOMPSON, The VLSI Complexity of Sorting, IEEE Trans. on Computers, vol. C-32, 1983
28. J. D. ULLMAN, Computational Aspect of VLSI, Computer Science Press, 1984
29. H. YASURA, N. TAGAKI, AND S. YAJIMA, The parallel Enumeration Sorting Scheme for VLSI, IEEE Trans. on Computers, vol. C-31, 1982, pp. 1192-1201