A scalable packet sorting circuit for high-speed WFQ packet scheduling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 7, 2008, Pages 781-791

  McLaughlin, K ^a   Sezer, S ^a   Blume, H ^b   Yang, X ^a   Kupzog, F ^b   Noll, T ^b  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Internet packet scheduling; Lookup, quality of service (QoS); Time stamp sorting; Traffic management; Weighted fair queueing (WFQ)

Indexed keywords

INTERNET; NONMETALS; PACKET NETWORKS; QUALITY OF SERVICE; SCHEDULING; SILICON; SPEED; TELECOMMUNICATION SYSTEMS;

40 GB/S; HIGH SPEEDS; INTERNET PROTOCOL (UP); IP SERVICE (CO); MATCHING CIRCUITRY; MEMORY LAYOUT; PACKET SCHEDULER (PS); PACKET SCHEDULING; QUALITY OF SERVICE (QOS); SEARCH TREES; SILICON TECHNOLOGIES; WEIGHTED FAIR QUEUEING (WFQ);

INTERNET PROTOCOLS;

EID: 48149099928     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000323     Document Type: Article

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