Wafer-scale integration of analog neural networks

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2008, Pages 431-438

  Schemmel, Johannes ^a   Fieres, Johannes ^a   Meier, Karlheinz ^a  

^a UNIVERSITY OF HEIDELBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; IMAGE CLASSIFICATION; NEURONS; ROUTING ALGORITHMS; SIGNAL PROCESSING; VEGETATION;

ANALOG NEURAL NETWORKS; ARTIFICIAL NEURAL NETWORKS; COMMUNICATION BANDWIDTHS; CONTINUOUS TIMES; LOW VOLTAGES; NETWORK MODELS; NOVEL DESIGNS; POWER CONSUMPTIONS; PROGRAMMABLE NETWORKS; REAL TIMES; RESOURCE USAGES; ROUTING SCHEMES; SYSTEM INTEGRATIONS; TOTAL POWER CONSUMPTIONS; VLSI IMPLEMENTATIONS; WAFER-SCALE INTEGRATIONS;

NEURAL NETWORKS;

EID: 56349166622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2008.4633828     Document Type: Conference Paper

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