A Design of a Compact 2GHz-PLL with a New Adaptive Active Loop Filter Circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 185-188

  Toyama, Masaomi ^a   Dosho, Shiro ^a   Yanagisawa, Naoshi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; BANDWIDTH; CAPACITANCE; JITTER; PHASE LOCKED LOOPS;

ACTIVE LOOP FILTERS;

ACTIVE FILTERS;

EID: 0141649445     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. Ian A. Young, Jeffrey K. Greason and Keng L. Wong", A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 11, NOVEMBER 1992,pp1599-1607
3. Jan Craninckx and Michel Steyaert,"A fully integrated CMOSDCS-1800 frequency synthesizer",IEEE Journal of Solid-State Circuits, vol. 33, December 1998,pp. 2054-2065
4. John G. Maneatis,"Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 11, NOVEMBER 1996, pp1723-1732
5. Masaitsu Nakajima, et al, "A 400MHz 32b Embedded Microprocessor Core AM34-1 with 4.0GB/S Cross-Bar Bus Switch for SoC", ISSCC DIGEST OF TECHNICAL PAPERS 2002, pp342-343