Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 5155-5158

  Ker, Ming Dou ^a   Wu, Chien Hua ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COST EFFECTIVENESS; PRODUCT DESIGN; TELECOMMUNICATION LINKS; TIME DELAY;

CIRCUIT COMPLEXITY; DATA RECOVERY; FLAT-PANEL-DISPLAY (FPD) LINKS;

SIGNAL RECEIVERS;

EID: 34547301290     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. IEEE standard for low-voltage differential signaling (LVDS) for scalable coherent interface (SCI), 1596.3 SCI-LVDS standard, IEEE Std. 1596.3-1996, 1994.
2. S. Kim et al., "An 800 Mbps multi-channel CMOS serial link with 3X oversampling," in Proc. of IEEE Custom Intergrated Circuits Conference, 1995, pp. 451-454.
3. S.-H. Lee et al., "A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit," IEEE J. Solid-State Circuits, vol. 37, pp. 1822-1830, 2002.
4. Y. Miki et al., "A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking," IEEE J. Solid-State Circuits, vol. 39, pp. 613-621, 2004.
5. LVDS 24-Bit Color Flat Panel Display Link, DS90CF581/DS90CF582 National Semiconductor Corp., 1997.
6. A. Boni, A. Pierazzi, and D. Vecchi, "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 706-711, 2004.
7. J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased, techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, 1996.