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Volumn , Issue , 2008, Pages 648-651

A serial communication infrastructure for multi-chip address event systems

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION; COMPUTER NETWORKS; LAPTOP COMPUTERS; TECHNICAL PRESENTATIONS;

EID: 51749084209     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541501     Document Type: Conference Paper
Times cited : (53)

References (18)
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    • R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. J. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, AER building blocks for multi-layer multi-chip neuromorphic vision systems, in Advances in Neural Information Processing Systems, S. Becker, S. Thrun, and K. Obermayer, Eds., 15. MIT Press, Dec 2005.
    • R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. J. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, "AER building blocks for multi-layer multi-chip neuromorphic vision systems," in Advances in Neural Information Processing Systems, S. Becker, S. Thrun, and K. Obermayer, Eds., vol. 15. MIT Press, Dec 2005.
  • 8
    • 0004189556 scopus 로고
    • VLSI analogs of neuronal visual processing: A synthesis of form and function,
    • Ph.D. dissertation, Department of Computation and Neural Systems, California Institute of Technology, Pasadena, CA
    • M. Mahowald, "VLSI analogs of neuronal visual processing: a synthesis of form and function," Ph.D. dissertation, Department of Computation and Neural Systems, California Institute of Technology, Pasadena, CA., 1992.
    • (1992)
    • Mahowald, M.1
  • 9
    • 0033740171 scopus 로고    scopus 로고
    • Point-to-point connectivity between neuromorphic chips using address events
    • May
    • K. A. Boahen, "Point-to-point connectivity between neuromorphic chips using address events," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 5, pp. 416-434, May 2000, http://www.neuroengineering.upenn.edu/publications/-papers/kwabena/BoahenAER2. pdf.
    • (2000) IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing , vol.47 , Issue.5 , pp. 416-434
    • Boahen, K.A.1
  • 14
    • 51749094442 scopus 로고    scopus 로고
    • SATA - Serial ATA
    • "SATA - Serial ATA," http://www.sata-io.org/.
  • 15
    • 51749097392 scopus 로고    scopus 로고
    • SDCC, Small Device C Compiler
    • "SDCC - Small Device C Compiler," http://sdcc.sourceforge.net/.
  • 16
    • 51749087324 scopus 로고    scopus 로고
    • Texas Instruments, Ti TLK3101 data sheet, http://www.ti.com/.
    • Texas Instruments, "Ti TLK3101 data sheet," http://www.ti.com/.
  • 17
    • 0029720957 scopus 로고    scopus 로고
    • A vlsi communication architecture for stochastically pulse-encoded analog signals
    • IEEE Press, May
    • A. Abusland, T. S. Lande, and M. Hovin, "A vlsi communication architecture for stochastically pulse-encoded analog signals," in IEEE International Symposium on Circuits and Systems, vol. III. IEEE Press, May 1996, pp. 401-404.
    • (1996) IEEE International Symposium on Circuits and Systems , vol.3 , pp. 401-404
    • Abusland, A.1    Lande, T.S.2    Hovin, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.