A slew controlled LVDS output driver circuit in 0.18μm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 2, 2009, Pages 538-548

  Tajalli, Armin ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

CMOS integrated circuits; Current mode logic (CML); Low voltage differential signaling (LVDS); Output driver; Source coupled logic (SCL)

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMITTER COUPLED LOGIC CIRCUITS; LOW POWER ELECTRONICS; TIMING CIRCUITS;

COMMON MODE VOLTAGE; CURRENT MODE LOGIC; IMPEDANCE MISMATCH; LOW SUPPLY VOLTAGES; LOW VOLTAGE DIFFERENTIAL SIGNALING; OUTPUT DRIVERS; OUTPUT VOLTAGE SWINGS; SOURCE COUPLED LOGIC;

CAPACITANCE;

EID: 59349105737     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2010788     Document Type: Article

References (17)

1. E. Yeung and M. A. Horowitz, "A 2.4 Gb/s/pin simultaneous bidirectional parallel link with, pre-pin skew compensation," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1619-1628, Dec. 2000.
2. A. Tajalli, P. Muller, and Y. Leblebici, "A power-efficient clock and data recovery circuit in 0.18-μm CMOS technology for multi-channel short-haul optical data communication," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2235-2244, Oct. 2007.
3. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Std 1596.3-1996, Mar. 1996.
4. Chapter 1: Introduction to LVDS [Online]. Available: http://lvds. national.com
5. V. Bratov, J. Binkley, V. Katzman, and J. Choma, "Architecture and implementation of a low-power LVDS output buffer for high-speed applications," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 10, pp. 2101-2108, Oct. 2005.
6. S. Jamasb et al., "A 622 MHz stand-alone LVDS driver pad in 0.18-μm CMOS," in Proc. IEEE Midwest Conf. Circuits and Systems (MWSCAS), 2001, vol. 2, pp. 610-613.
7. Y. Yan and T. H. Szymanski, "Low power high speed I/O interface in 0.18-μm CMOS," in Proc. IEEE ICECS, Dec. 2003.
8. M. Chen et al., "Low-voltage low-power LVDS driver," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 472-479, Feb. 2005.
9. M. Bartolini et al., "A reduced output ringing CMOS buffer," IEEE Trans. Circuits Syst. II: Express Briefs, vol. 54, no. 2, pp. 102-106, Feb. 2007.
10. T. Gabara et al., "LVDS I/O buffers with a controlled reference circuit," in Proc. IEEE ASIC Conf., Sep. 1997, pp. 311-315.
11. S. Galal and B. Razavi, "10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2138-2146, Dec. 2003.
12. T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of timing jitter in CMOS ring oscillators," in Proc. ISCAS, May 1994, vol. 4, pp. 27-30.
13. A. Boni et al., "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
14. G. Mandal and P. Mandal, "Low power LVDS transmitter with low common mode variation for 1 Gb/s-per pin operation," in Proc. ISCAS, May 2004, vol. I, pp. 1120-1123.
15. A. Tajalli and Y. Leblebici, "A power-efficient LVDS driver circuit in 0.18-μm CMOS technology," in Proc. Ph.D. Research in Microelectronics and Electronics Conf. (PRIME), Jul. 2007, pp. 145-148.
16. C. H. Doan, "Design and implementation of a highly-integrated low-power CMOS frequency synthesizer for an indoor wireless wide-band-CDMA direct-conversion receiver," Masters thesis, Electr. Eng. Comput. Sci. Dept., Univ. California, Berkeley, 2000.
17. B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2004.