Fault model and test procedure for phase change memory

IET Computers and Digital Techniques

Volumn 5, Issue 4, 2011, Pages 263-270

  Mohammad, M G ^a  

^a KUWAIT UNIVERSITY   (Kuwait)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PROCESS; FAULT MODEL; FAULT PRIMITIVE; MEMORY TECHNOLOGY; NON-VOLATILE MEMORIES; TEST ALGORITHMS; TEST PROCEDURES;

ALGORITHMS; FAILURE ANALYSIS; FLASH MEMORY; METALLIC COMPOUNDS; MOS DEVICES; TESTING;

PHASE CHANGE MEMORY;

EID: 79960264441     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2010.0083     Document Type: Article

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