Status and challenges of PCM modeling

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 214-221

  Lacaita, A L ^a,b   Ielmini, D ^a  

^a POLITECNICO DI MILANO   (Italy)

^b IFN CNR   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS MATERIALS; CHALCOGENIDES; CIRCUIT SIMULATION; FLASH MEMORY; NONVOLATILE STORAGE; READOUT SYSTEMS;

ELECTROTHERMAL MODELING; READOUT RESISTANCE;

PHASE CHANGE MEMORY;

EID: 39549084074     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430917     Document Type: Conference Paper

References (22)

1. S. R. Ovshinsky, "Reversible electrical switching phenomena in disordered structures," Phys. Rev. Lett., vol. 21, pp. 1450-1453, 1968.
2. S. J. Ahn, Y. J. Song, C. W. Jeong, J. M. Shin, Y. Fai, Y. N. Hwang, S. H. Lee, K. C. Ryoo, S. Y. Lee, J. H. Park, H. Horii, Y. H. Ha, J. H. Yi, B. J. Kuh, G. H. Koh, G. T. Jeong, H. S. Jeong, K. Kim, and B. I. Ryu, "Highly manufacturable high density phase change memory of 64Mb and beyond," in IEDM Tech. Dig., pp. 907-910, 2004.
3. F. Pellizzer, A. Benvenuti, B. Gleixner, Y. Kim, B. Johnson, M. Magistretti, T. Marangon, A. Pirovano, R. Bez, and G. Atwood, "A 90nm phase change memory technology for stand-alone non-volatile memory applications," in Symp. VLSI Tech. Dig., pp. 122-123, 2006.
4. Y. C. Chen, C. T. Rettner, S. Raoux, G. W. Burr, S. H. Chen, R. M. Shelby, M. Salinga, W. P. Risk, T. D. Happ, G. M. McClelland, M. Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, T. Nirschl, M. Lamorey, C. F. Chen, E. Joseph, S. Zaidi, B. Yee, H. L. Lung, R. Bergmann and C. Lam, "Ultra-thin phase-change bridge memory device using GeSb," in IEDM Tech. Dig., 777-780, 2006.
5. H. Horii, J. H. Yi, J. H. Park, Y. H. Ha, I. G. Baek, S. O. Park, Y. N. Hwang, S. H. Lee, Y. T. Kim, K. H. Lee, U-In Chung and J. T. Moon, "A novel cell technology using N-doped GeSbTe films for phase change RAM," in Symp. on VLSI Tech. Dig., 177-178, 2003.
6. 5 phase-change memory cells featuring 1.5-V/100-μA standard 0.13"m CMOS operations," in IEDM Tech. Dig., 738-741, 2005.
7. S. Lai, "Current status of the phase change memory and its future," in IEDM Tech. Dig., pp. 255-258, 2003.
8. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez, "Scaling analysis of phase-change memory technology," in IEDM Tech. Dig., pp. 699-702, 2003.
9. N. Takaura, M. Terao, K. Kurotsuchi, T. Yamauchi, O. Tonomura, Y. Hanaoka, R. Takemura, K. Osada, T. Kawahara, and H. Matsuoka, "A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations," IEDM Tech. Dig., 897, 2003.
10. M. H. Cohen, H. Fritzsche and S. R. Ovshinsky, "Simple band model for amorphous semiconducting alloys," Phys. Rev. Lett. 22, 1065-1068, 1969.
11. D. Ielmini and Y. Zhang, "Physics-based analytical model of chalcogenide-based memories for array simulation," IEDM Tech. Dig., 401-404, 2006.
12. D. Ielmini and Y. Zhang, "Evidence for trap-limited transport in the sub-threshold conduction regime of chalcogenide glasses," Appl. Phys. Lett. 90, 192102, 2007.
13. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer and R. Bez, "Electronic switching in phase-change memories," IEEE Trans. Electron Devices 51, 452-459, 2004.
14. A. Pirovano, A. Redaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita and R. Bez, "Reliability study of phase change nonvolatile memories," IEEE Trans. Dev. Mater. Reliab. 4, 422, 2004.
15. F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, "Novel utrench phase-change memory cell for embedded and stand-alone non-volatile memory applications," in Symp. on VLSI Tech. Dig., pp. 18-19, 2004.
16. Y. Song, K. Ryoo, Y. Hwang, C. Jeong, D. Lim, S. Park, J. Kim, S. Lee, J. Kong, S. Ahn, J. Park, J. Oh, Y. Oh, J. Shin, Y. Fai, G. Koh, G. Jeong, R. Kim, H. Lim, I. Park, H. Jeong, K. Kim, "Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology," in Symp. VLSI Tech. Dig., pp. 118-119, 2006.
17. R. Bergmann, M. Breitwisch, G. W. Burr, R. Cheek, C. F. Chen, S. H. Chen, Y. C. Chen, T. D. Happ, C. H. Ho, E. Joseph, C. Lam, M. Lamorey, M. H. Lee, H. L. Lung, T. Nirschl, J. B. Philipp, S. Raoux, A. Schrott, B. Yee, S. Zaidi, "Novel One-Mask Self-Heating Pillar Phase Change Memory," in Symp. VLSI Tech. Dig., pp. 120-121, 2006.
18. U. Russo, A. Redaelli, D. Ielmini and A. L. Lacaita, "Geometry and material optimization for programmng current scaling in phase-change memory," International Conference on Memory Technology and Design, ICMTD 2007.
19. Y. N. Hwang, S. H. Lee, S. J. Ahn, S. Y. Lee, K. C. Ryoo, H. S. Hong, H. C. Koo, F. Yeung, J. H. Oh, H. J. Kim, W. C. Jeong, J. H. Park, H. Horii, Y. H. Ha, J. H. Yi, G. H. Koh, G. T. Jeong, H. S. Jeong and K. Kim, "Writing current reduction for high-density phase-change RAM," IEDM Tech. Dig. 893, 2003.
20. ITRS 2006 Update, available online at www.public.itrs.net
21. A. Redaelli, D. Ielmini, U. Russo and A. L. Lacaita, "Intrinsic data retention in nanoscaled phase-change memories - Part II: Statistical analysis and prediction of failure time," IEEE Trans. Electron Devices 53, 3040, 2006.
22. D. Ielmini, A. L. Lacaita and D. Mantegazza, "Recovery and drift dynamics of resistance and threshold voltages in phase-change memories," IEEE Trans. Electron Devices 54, 308, 2007.