SILC-based reassignment of trapping and trap generation regimes of positive bias temperature instability

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2011, Pages

  Yang, J Q ^a,b   Masuduzzman, M ^a   Kang, J F ^b   Alam, M A ^a  

^a PURDUE UNIVERSITY   (United States)

^b PEKING UNIVERSITY   (China)

Author keywords

positive bias temperature instability (PBTI); stress induced leakage current (SILC); Trap Generation; Trapping

Indexed keywords

POSITIVE BIAS TEMPERATURE INSTABILITIES; SIGN REVERSAL; STRESS INDUCED LEAKAGE CURRENT (SILC); STRESS-INDUCED LEAKAGE CURRENT; THEORETICAL MODELS; THRESHOLD VOLTAGE SHIFTS; TRAP GENERATION; TRAPPING;

BIAS VOLTAGE; THRESHOLD VOLTAGE;

INTEGRATED CIRCUITS;

EID: 79959296592     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2011.5784476     Document Type: Conference Paper

References (21)

1. A. Kerber and E. Cartier, "Reliability challenges for CMOS technology qualifications with Hafnium Oxide/Titanium Nitride gate stacks," IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 147-162, 2009.
2. D. Ioannou, S. Mittl, and G. La Rosa, "Positive Bias Temperature Instability effects in nMOSFETs with HfO2/TiN gate stacks," IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 128-134, 2009.
3. E. Cartier and A. Kerber, "Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress," in Proc. Int. Rel. Phys. Symp., 2009, pp. 486-492.
4. A. Kerber, K. Maitra, A. Majumdar, M. Hargrove, R. Carter, and E. Cartier, "Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2/TiN gate stacks," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3175-3183, 2008.
5. G. Bersuker et al., "Mechanism of Electron Trapping and Characteristics of Traps in HfO2 Gate Stacks," IEEE Trans. Device Mater. Rel., vol. 7, no. 1, pp. 138-145, 2007.
6. K. Zhao, J. Stathis, A. Kerber, and E. Cartier, "PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks," in Proc. Int. Rel. Phys. Symp., 2010, pp. 50-54.
7. C. Young et al., "Electron trap generation in high-k gate stacks by constant voltage stress," IEEE Trans. Device Mater. Rel.,, vol. 6, no. 2, pp. 123-131, 2006.
8. M. Rafik, G. Ribes, and G. Ghibaudo, "Contributions and limits of charge pumping measurement for addressing trap generation in high-k/SiO2 dielectric stacks," in Proc. Int. Rel. Phys. Symp., 2008, pp. 341-346.
9. S. Pae et al., " Characterization of SILC and its end-of-line reliability assessment of 45nm high-k and metal-gate technology," in Proc. Int. Rel. Phys. Symp., 2009, pp. 499-504.
10. M. Masuduzzaman, A. Islam, and M. Alam, "Exploring the capability of multifrequency Charge Pumping in resolving location and energy levels of traps within dielectric," IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3421-3431, 2008.
11. A. Islam, V. Maheta, H. Das, S. Mahapatra, and M. Alam, "Mobility degradation due to interface traps in plasma oxynitride PMOS devices," in Proc. Int. Rel. Phys. Symp., 2008, pp. 87-96.
12. S. Sahhaf, R. Degraeve, P. Roussel, B. Kaczer, T. Kauerauf, and G. Groeseneken, "A new TDDB reliability prediction methodology accounting for multiple SBD and wear out," IEEE Trans. Electron Devices, vol. 56, no. 7, pp. 1424-1432, 2009.
13. S. Zafar, A. Kumar, E. Gusev, and E. Cartier, "Threshold voltage instabilities in high-κ gate dielectric stacks," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45-64, 2005.
14. K. Sakakibara, N. Ajika, M. Hatanaka, and H. Miyoshi, "A quantitative analysis of stress induced excess current (SIEC) in SiO2 films," in Proc. Int. Rel. Phys. Symp., 1996, pp. 100-107.
15. S. Deora, V. Maheta, A. Islam, M. Alam, and S. Mahapatra, "A common framework of NBTI generation and recovery in plasma-nitrided SiON p-MOSFETs," IEEE Electron Device Lett., vol. 30, no. 9, pp. 978-980, 2009.
16. S. Mahapatra, V. Maheta, A. Islam, and M. Alam, "Isolation of NBTI stress generated interface trap and hole-trapping components in PNO p-MOSFETs," IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 236-242, 2009.
17. Y. Yasuda, T.-J. Liu, and C. Hu, "Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 417-422, 2008.
18. P. Magnone, F. Crupi, L. Pantisano, and C. Pace, "Fermi-level pinning at polycrystalline silicon-HfO[sub 2] interface as a source of drain and gate current 1/f noise," Applied Physics Letters, vol. 90, no. 7, p. 073507, 2007.
19. D. Heh, C. Young, and G. Bersuker, "Experimental evidence of the fast and slow charge trapping/detrapping processes in High- k dielectrics subjected to PBTI stress," IEEE Electron Device Lett., vol. 29, no. 2, pp. 180-182, 2008.
20. J. Mitard et al., "Large-scale time characterization and analysis of PBTI In HfO2/metal gate stacks," in Proc. Int. Rel. Phys. Symp., 2006, pp. 174-178.
21. S. Zafar et al., "A comparative study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates," in VLSI Symp. Tech. Dig., 2006, pp. 23-25.