메뉴 건너뛰기




Volumn , Issue , 2009, Pages 499-504

Characterization of SILC and its end-of-life reliability assessment on 45nm high-K and metal-gate technology

Author keywords

High K dielectric; Metal gate; NMOS PBTI; Reliability; SILC; TDDB; Transistor

Indexed keywords

HIGH-K DIELECTRIC; METAL GATE; NMOS PBTI; SILC; TDDB;

EID: 70449107015     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2009.5173303     Document Type: Conference Paper
Times cited : (15)

References (10)
  • 1
    • 50249185641 scopus 로고    scopus 로고
    • A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
    • K. Mistry et al., "A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," in IEDM Tech. Dig., 2007, pp. 247-250.
    • (2007) IEDM Tech. Dig , pp. 247-250
    • Mistry, K.1
  • 2
    • 64549151943 scopus 로고    scopus 로고
    • 2 SRAM Cell Size in a 291Mb Array
    • 2 SRAM Cell Size in a 291Mb Array," in IEDM Tech. Dig., 2008.
    • (2008) IEDM Tech. Dig
    • Natarajan, S.1
  • 3
    • 51549107155 scopus 로고    scopus 로고
    • BTI reliability of 45 nm high-K + metal-gate process technology
    • S. Pae et al., "BTI reliability of 45 nm high-K + metal-gate process technology," in International Reliability Physics Symp. Proc., 2008, pp. 352-357.
    • (2008) International Reliability Physics Symp. Proc , pp. 352-357
    • Pae, S.1
  • 4
    • 51549120610 scopus 로고    scopus 로고
    • Dielectric breakdown in 45 nm high-k/metal gate process technology
    • C. Prasad et al., "Dielectric breakdown in 45 nm high-k/metal gate process technology," in International Reliability Physics Symp. Proc., 2008, pp. 667-668.
    • (2008) International Reliability Physics Symp. Proc , pp. 667-668
    • Prasad, C.1
  • 5
    • 67650332617 scopus 로고    scopus 로고
    • 2/TiN gate stacks during positive bias temperature stress, International Reliability Physics Symp. Proc
    • to be published
    • 2/TiN gate stacks during positive bias temperature stress," International Reliability Physics Symp. Proc., to be published, 2009.
    • (2009)
    • Cartier, E.1
  • 6
    • 67650443125 scopus 로고    scopus 로고
    • TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates, International Reliability Physics Symp. Proc
    • to be published
    • A. Kerber et al., "TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates," International Reliability Physics Symp. Proc., to be published, 2009.
    • (2009)
    • Kerber, A.1
  • 8
    • 20444463961 scopus 로고    scopus 로고
    • 2-based high-k gate dielectrics
    • 2-based high-k gate dielectrics," in IEDM Tech. Dig., 2004, pp. 129-132.
    • (2004) IEDM Tech. Dig , pp. 129-132
    • Torii, K.1
  • 10
    • 57849087524 scopus 로고    scopus 로고
    • 45nm Transistor Reliability
    • J. Hicks et al., "45nm Transistor Reliability," Intel Technology Journal, vol. 12, Issue 02, pp. 131-144, 2008.
    • (2008) Intel Technology Journal , vol.12 , Issue.2 , pp. 131-144
    • Hicks, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.