Mechanism of electron trapping and characteristics of traps in HfO 2 gate stacks

IEEE Transactions on Device and Materials Reliability

Volumn 7, Issue 1, 2007, Pages 138-145

  Bersuker, Gennadi ^a   Sim, J H ^a   Park, Chang Seo ^a   Young, Chadwin D ^a   Nadkarni, Suvid V ^b   Choi, Rino ^a   Lee, Byoung Hun ^a  

^a SEMATECH   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Electron trapping; High dielectrics; Threshold voltage instability

Indexed keywords

DEFECTS; ELECTRIC POTENTIAL; ELECTRON TRAPS; HAFNIUM COMPOUNDS; MOSFET DEVICES; OXYGEN VACANCIES; RESONANT TUNNELING; STRESS ANALYSIS; TRANSISTORS;

ELECTRON TRAPPING; GATE STACKS; NMOS TRANSISTORS; THRESHOLD VOLTAGE INSTABILITY;

GATE DIELECTRICS;

EID: 34547195141     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.897532     Document Type: Conference Paper

References (17)

1. G. Bersuker, B. H. Lee, and H. R. Huff, "Novel dielectric materials for future transistor generations," Int. J. High Speed Electron. Syst., vol. 16, no. 1, pp. 221-239, Mar. 2006.
2. 2 gate dielectrics," in Proc. 41st IEEE Int. Reliab. Phys. Symp., 2003, pp. 41-44.
3. J. H. Sim, R. Choi, Y. H. Lee, C. Young, P. Zeitzoff, D. L. Kwong, and G. Bersuker, "Trapping/de-trapping gate bias dependence of Hf-silicate dielectrics with poly and TiN gate electrode," Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2420-2423, 2005.
4. S. Zafar, A. Kumar, E. Gusev, and E. Cartier, "Threshold voltage instabilities in high-κ gate dielectric stacks," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45-64, Mar. 2005.
5. C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumor, and F. Martin, "Characterization and modeling of hysteresis phenomena in high-κ dielectrics," in IEDM Tech. Dig., 2004, pp. 737-740.
6. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-κ dielectrics reliability issues," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 5-19, Mar. 2005.
7. M. A. Alam. and S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microel. Reliab., vol. 45, no. 1, p. 71, Jan. 2005.
8. R. Choi, S. J. Rhee, B. H. Lee, J. C. Lee, and G. Bersuker, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," IEEE Electron Device Lett., vol. 26, no. 3, pp. 197-199, Mar. 2005.
9. t instability and charge trapping using ultra-short pulse in characterization," in Proc. 43rd Annu. IEEE Int. Rel. Phys. Symp., 2005, pp. 75-79.
10. G. Bersuker, P. Zeitzoff, J. Sim, B. H. Lee, R. Choi, G. Brown, and C. Young, "Mobility evaluation in transistors with charge trapping gate dielectrics," Appl. Phys. Lett., vol. 87, no. 4, p. 042905, Jul. 2005.
11. D. Heh, R. Choi, C. D. Young, and G. Bersuker, "Fast and slow charge trapping/detrapping processes in high-κ nMOSFETs," in Proc. IEEE IRW Final Report, 2006, pp. 120-124.
12. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. M. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, "Effect of pre-existing defects on reliability assessment of high-κ gate dielectrics," Microelectron. Reliab., vol. 44, no. 9-11, pp. 1509-1512, Sep.-Nov. 2004.
13. G. Ribes, M. Muller, S. Bruyere, D. Roy, M. Denais, V. Huard, T. Skotnicki, and G. Ghibaudo, "Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques," in Proc. Eur. Solid-State Device Res. Conf., 2004, pp. 89-92.
14. G. Bersuker, B. H. Lee, H. R. Huff, J. Gavartin, and A. Shluger, "Mechanism of charge trapping reduction in scaled high-κ gate stacks," in Defects in High-κ Materials, E. Gusev, Ed. New York: Springer-Verlag, 2006, p. 227.
15. J. Gavartin and A. Shluger, "Ab initio modeling of electron-phonon coupling in high-κ dielectrics," Phys. Stat. Sol. C, vol. 3, no. 10, 2006.
16. 2 as charge traps in high-κ gate stack," Appl. Phys. Lett., vol. 89, no. 8, p. 082908, Aug. 2006.
17. 2 : Theoretical insight," ECS Trans., vol. 3, no. 3, pp. 277-290, 2006.