Experimental evidence of the fast and slow charge trapping/detrapping processes in high-κ dielectrics subjected to PBTI stress

IEEE Electron Device Letters

Volumn 29, Issue 2, 2008, Pages 180-182

  Heh, Dawei ^a   Young, Chadwin D ^a   Bersuker, Gennadi ^a  

^a SEMATECH   (United States)

Author keywords

Discharge; Electron trapping; High ; Single pulse; Transient charge

Indexed keywords

CHARGE TRAPPING; DIELECTRIC MATERIALS; ELECTRON TRAPS; THERMODYNAMIC STABILITY;

CHARGE DETRAPPING; ELECTRON TRAPPING; POSITIVE BIAS TEMPERATURE INSTABILITY; TRANSIENT CHARGE;

MOSFET DEVICES;

EID: 39549093112     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.914088     Document Type: Article

References (18)

1. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
2. M. Houssa, L. Pantisano, L.-A. Ragnarsson, R. Degraeve, T. Schram, G. Pourtois, S. D. Gendt, G. Groeseneken, and M. M. Heyns, "Electrical properties of high-k gate dielectrics: Challenges, current issues, and possible solutions," Mater. Sci. Eng. R: Rep., vol. 51, pp. 37-85, 2006.
3. 2 gate dielectrics resulting in improved scaling and electron mobility," J. Appl. Phys., vol. 99, no. 2, pp. 023508-1-023508-8, 2006.
4. 2 gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 5, pp. 339-341, May 2003.
5. D. Heh, R. Choi, C. D. Young, B. H. Lee, and G. Bersuker, "A novel bias temperature instability characterization methodology for high-k nMOSFETs," IEEE Electron Device Lett., vol. 27, no. 10, pp. 849-851, Oct. 2006.
6. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. M. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, "Effect of pre-existing defects on reliability assessment of high-k gate dielectrics," Microelectromech. Rel., vol. 44, pp. 1509-1512, 2004.
7. R. Choi, S. J. Rhee, J. C. Lee, B. H. Lee, and G. Bersuer, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," IEEE Electron Device Lett., vol. 26, no. 3, pp. 197-199, Mar. 2005.
8. R. Choi, S. C. Song, C. D. Young, G. Bersuker, and B. H. Lee, "Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique," Appl. Phys. Lett., vol. 87, pp. 122901-122903, 2005.
9. M. Denais, C. Parthasarathy, G. Ribes, Y. Rey-Tauriac, N. Revil, A. Bravaix, V. Huard, and F. Perrier, "On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's," in IEDM Tech. Dig., 2004, pp. 109-112.
10. g," IEEE Electron Device Lett., vol. 26, no. 8, pp. 586-589, Aug. 2005.
11. 2 gate dielectrics," in Proc. Int. Rel. Phys. Symp., 2003, pp. 41-45.
12. 2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs," in IEDM Tech. Dig., 2004, pp. 733-736.
13. 2 NMOS transistors," in Proc. Int. Rel. Phys. Symp., 2006, pp. 179-183.
14. 2 gate stacks," IEEE Trans. Device Mater. Rel., vol. 7, no. 1, pp. 138-145, Mar. 2007.
15. J. Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, J. J. Peterson, S. Gopalan, B. Foran, H.-J. Li, B. H. Lee, G. Bersuker, P. Zeitzoff, G. A. Brown, P. Lysaght, C. D. Young, R. W. Murto, and H. R. Huff, "Experimental study of etched back thermal oxide for optimization of the Si/high-k interface," in Proc. 2004 Spring Meeting Mater. Res. Soc., p. E1.A.1.
16. D. Heh, R. Choi, C. D. Young, and G. Bersuker, "Fast and slow charge trapping/detrapping processes in high-k nMOSFETs," in Proc. Int. Integr. Rel. Workshop, 2006, pp. 120-124.
17. B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeitzoff, R. W. Murto, L. Larson, and C. Ramiller, "Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)," in IEDM Tech. Dig., 2004, pp. 859-862.
18. D. Heh, G. Bersuker, R. Choi, C. D. Young, and B. H. Lee, "A novel bias temperature instability characterization methodology for high-k MOSFETs," in Proc. Eur. Solid-State Device Res. Conf., 2006, pp. 387-390.