Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON

IEEE Transactions on Electron Devices

Volumn 55, Issue 1, 2008, Pages 417-422

  Yasuda, Yuri ^a,b   Liu, Tsu Jae King ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Analog; Flicker noise (1 f noise); Hafnium silicon oxynitride (HfSiON); Mixed signal

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; SPURIOUS SIGNAL NOISE;

FLICKER-NOISE; HAFNIUM SILICON OXYNITRIDE; MIXED SIGNAL;

CMOS INTEGRATED CIRCUITS;

EID: 37749021901     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.910759     Document Type: Article

References (27)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
2. S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chart, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Slufren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
3. J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High-k dielectrics and MOSFET characteristics," in IEDM Tech. Dig., Dec. 2003, pp. 95-98.
4. M. Koike, T. Ino, Y. Kamimuta, M. Koyama, Y. Kamata, M. Suzuki, Y. Mitani, A. Nishiyama, and Y. Tshunashima, "Effect of Hf-N bond on properties of thermally stable amorphous HfSiON and applicability of this material to sub-50 nm technology node LSIs," in IEDM Tech. Dig. Dec. 2003, pp. 107-110.
5. 2 high-k dielectric," in IEDM Tech. Dig., Dec. 2000, pp. 35-38.
6. K. Kojima, R. Iijima, T. Ohguro, T. Watanabe, M. Takayanagi, H. S. Momose, K. Ishimaru, and H. Ishiuchi, "HfSiON gate dielectrics design for mixed signal CMOS," in VLSI Symp. Tech. Dig., 2005, pp. 58-59.
7. 3 and HfAlOx gate stacks," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1679-1687, Oct. 2004.
8. Y. Yasuda, C.-H. Lin, T.-J. King, and C. Hu, "Impact of HfSiON induced flicker noise on scaling of future mixed-signal CMOS," in VLSI Symp. Tech. Dig., 2006, pp. 130-131.
9. T. Contaret, K. Romanjek, T. Boutchacha, and F. Boeuf, "Low frequency noise characterization and modeling in ultrathin oxide MOSFETs," Solid State Electron., vol. 50, no. 1, pp. 63-68, 2005.
10. T. Contaret, T. Boutchacha, G. Ghibaudo, F. Boeuf, and T. Skotnicki, "Low frequency noise in biaxially strained silicon n-MOSFETs with ultrathin gate oxides," Solid State Electron., vol. 51, no. 4, pp. 633-637, 2007.
11. A. K. M. Ahsan and S. Ahmed, "Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface," Solid State Electron., vol. 50, no. 11/12, pp. 1705-1709, Nov./Dec. 2006.
12. N. Kimizuka, Y. Yasuda, T. Iwamoto, I. Yamamoto, K. Takano, Y. Akiyama, and K. Imai, "Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme," in VLSI Symp. Tech. Dig., 2005, pp. 218-219.
13. Y. Yasuda, N. Kimizuka, Y. Akiyama, Y. Yamagata, Y. Goto, and K. Imai, "System LSI multi-Vth transistors design methodology for maximizing efficiency of body-biasing control to reduce Vth variation and power consumption," in IEDM Tech. Dig., Dec. 2005, pp. 68-71.
14. H. Takeuchi, H. Y. Wong, D. Ha, and T.-J. King, "Impact of oxygen vacancies on lugh-k gate stack engineering," in IEDM Tech. Dig., Dec. 2004, pp. 829-832.
15. B. Min, S. P. Devireddy, and Z. Celik-Butler, "Low-frequency noise characteristics of HfSiON gate-dielectric metal-oxide-serm conductor-field-effect transistors," Appl. Phys. Lett., vol. 86, no. 8, p. 082 102, Feb.2005.
16. B. Min, S. P. Devireddy, Z. Celik-Butler, A. Shanware, L. Colombo, K. Green, J. J. Chambers, M. R. Visokay, and A. L. P. Rotandaro, "Impact of interfacial layer on low-frequency noise of HfSiON dielectric MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 6, pp. 1459-1466, Jun.2006.
17. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noisein metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.
18. S. Maeda, Y. S. Jin, J. A. Choi, S. Y. Oh, H. W. Lee, J. Y. Yoo, M. C. Sun, J. H. Ku, K. Lee, S. G. Bae, S. G. Kang, J. H. Yang, Y. W. Kim, and K. P. Sub, "Impact of mechanical stress engineering on flicker noise characteristics," in VLSI Symp. Tech. Dig., 2004, pp.102-103.
19. T. Ueno, H. S. Thee, H. Lee, M. D. Kim, H. S. Cho, H. S. Baik, Y. H. Jung, H. W. Lee, H. S. Park, C. K. Lee, G. J. Bae, and N. I. Lee, "Improved 1/f noise characteristics in locally strained Si CMOS using hydrogen-controlled stress liners and embedded SiGe," in VLSI Symp. Tech. Dig., 2006, pp. 128-129.
20. K. Narasimhulu, I. V. Setty, and V. R. Rao, "The effect of single-halo doping on the low-frequency noise performance of deep submicrometer MOSFETs," IEEE Electron Device Lett., vol. 27, no. 12, pp. 995-997, Dec. 2006.
21. C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and E Martin, "Characterization and modeling of hysteresis phenomena in high k dielectrics," in IEDM Tech. Dig., Dec. 2004, pp. 737-740.
22. B. S. Ju, S. C. Song, T. H. Lee, B. Sassman, C. Y. Kang, B. H. Lee, and R. Jammy, "A novel in situ plasma treatment for damage-free metal/high-k gate stack RIE process," in IEDM Tech. Dig., Dec. 2006, pp. 645-648.
23. T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, and T. Mogami, "A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes," in IEDM Tech. Dig., 2003, pp. 639-642.
24. M. S. Liang and C. Hu, "Electron trapping in very thin thermal silicon dioxides," in IEDM Tech. Dig., 1981, pp. 396-399.
25. M. H. Tsai and T. P. Ma, "The impact of device scaling on the current fluctuations in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2061-2068, Nov. 1994.
26. J. Ramos, E. Augendre, A. Kottantharayil, A. Mercha, E. Simoen, M. Rosmeulen, S. Severi, C. Kerner, T. Chiarella, A. Nackaerts, I. Ferain, T. Hoffmann, M. Jurczak, and S. Biesemans, "Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs," in Proc. 8th Int. Conf. Solid-State Integr. Circuit Technol., 2006, pp. 72-74.
27. Y. Yasuda and C. Hu, "Effect of fluorine incorporation on 1/f noise of HfSiON FETs for future mixed-signal CMOS," in IEDM Tech. Dig., 2006, p. 277-280.