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Volumn , Issue , 2011, Pages 431-436

Design of MRAM based logic circuits and its applications

Author keywords

3D integration; Flip flop; Fpga; Full adder; Magnetic logic; Memory in logic; Mram; Non volatile

Indexed keywords

3-D INTEGRATION; FLIP-FLOP; FPGA; FULL ADDERS; MAGNETIC LOGIC; MEMORY-IN-LOGIC; MRAM; NON-VOLATILE;

EID: 79957675679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1973009.1973104     Document Type: Conference Paper
Times cited : (29)

References (49)
  • 6
    • 78650005927 scopus 로고    scopus 로고
    • Phase change memory
    • Wong, H S P, et al., 2010, "Phase Change Memory", Proceedings of the IEEE, Vol.98, pp.2201-2227.
    • (2010) Proceedings of the IEEE , vol.98 , pp. 2201-2227
    • Wong, H.S.P.1
  • 7
    • 79959351464 scopus 로고    scopus 로고
    • USA
    • Kund, M et al., 2005, IEEE IEDM, USA, pp. 754-757.
    • (2005) IEEE IEDM , pp. 754-757
    • Kund, M.1
  • 8
    • 35748965560 scopus 로고    scopus 로고
    • The emergence of spin electronics in data storage
    • DOI 10.1038/nmat2024, PII NMAT2024
    • Chappert, C, Fert, A and Nguyen Van Dau, F, 2007, "The emergence of spin electronics in data storage" Nature Materials, Vol.6, pp.813-823. (Pubitemid 350050577)
    • (2007) Nature Materials , vol.6 , Issue.11 , pp. 813-823
    • Chappert, C.1    Fert, A.2    Van Dau, F.N.3
  • 9
    • 0035900398 scopus 로고    scopus 로고
    • Wolf, S et al., 2001, Science, Vol. 294, pp.1488-1495.
    • (2001) Science , vol.294 , pp. 1488-1495
    • Wolf, S.1
  • 10
    • 79957757469 scopus 로고    scopus 로고
    • Everspin. http://www.everspin.com/.
    • Everspin
  • 14
    • 42049103709 scopus 로고    scopus 로고
    • Parkin, S S P, et al, 2008, Science, Vol.320, pp190-194.
    • (2008) Science , vol.320 , pp. 190-194
    • Parkin, S.S.P.1
  • 15
    • 77957881968 scopus 로고    scopus 로고
    • 45nm low power CMOS logic compatible embedded STT-MRAM utilizing a reverse connection 1T/1MTJ cell
    • Lin, C J et al., 2009, "45nm Low power CMOS logic compatible embedded STT-MRAM utilizing a reverseconnection 1T/1MTJ cell" IEEE IEDM, pp.279-282.
    • (2009) IEEE IEDM , pp. 279-282
    • Lin, C.J.1
  • 18
    • 51849119169 scopus 로고    scopus 로고
    • Spin-MTJ based non-volatile flip-flop
    • Zhao, W S et al., 2007, "Spin-MTJ based Non-Volatile Flip- Flop" Proc. of IEEE-NANO, pp. 399-402.
    • (2007) Proc. of IEEE-NANO , pp. 399-402
    • Zhao, W.S.1
  • 21
    • 77957882846 scopus 로고    scopus 로고
    • A novel CuxSiyO resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications
    • Wang, M et al., 2010, "A Novel CuxSiyO Resistive Memory in Logic Technology with Excellent Data Retention and Resistance Distribution for Embedded Applications", IEEE Symp. Very Large Scale Integr. Technologys, pp. 89-90.
    • (2010) IEEE Symp. Very Large Scale Integr. Technologys , pp. 89-90
    • Wang, M.1
  • 23
  • 24
    • 70449421590 scopus 로고    scopus 로고
    • Spin Transfer Torque (STT)-MRAM based run time reconfiguration FPGA circuit
    • article 14
    • Zhao, W S et al. 2009, "Spin Transfer Torque (STT)-MRAM based Run Time Reconfiguration FPGA circuit" ACM Trans. on Embedded Computing Systems, 9, No.2, article 14.
    • (2009) ACM Trans. on Embedded Computing Systems , vol.9 , Issue.2
    • Zhao, W.S.1
  • 25
    • 54949130247 scopus 로고    scopus 로고
    • A non-volatile run-time FPGA using thermally assisted switching MRAMS
    • Guillemenet, Y et al., 2008, "A non-volatile run-time FPGA using thermally assisted switching MRAMS", Proc. Int. Conf. Field Programmable Logic Appl. pp. 421-426.
    • (2008) Proc. Int. Conf. Field Programmable Logic Appl. , pp. 421-426
    • Guillemenet, Y.1
  • 26
    • 70449359801 scopus 로고    scopus 로고
    • Fabrication of a non-volatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array
    • Kyoto, Japan
    • Suzuki, D et al., 2009, "Fabrication of a Nonvolatile Lookup- Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array", IEEE Symp. Very Large Scale Integr. (VLSI) Circuits, Kyoto, Japan, pp. 80-81.
    • (2009) IEEE Symp. Very Large Scale Integr. (VLSI) Circuits , pp. 80-81
    • Suzuki, D.1
  • 29
    • 77954521173 scopus 로고    scopus 로고
    • Design of embedded MRAM macros for memory-in-logic applications
    • USA
    • Chaudhuri, S et al., 2010, "Design of Embedded MRAM Macros for Memory-in-Logic Applications", Proc of ACM/IEEE GLSVLSI, USA, pp.155-158.
    • (2010) Proc of ACM/IEEE GLSVLSI , pp. 155-158
    • Chaudhuri, S.1
  • 30
    • 70449353237 scopus 로고    scopus 로고
    • TAS-MRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA
    • article 8
    • Zhao, W S et al. 2009, "TAS-MRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA", ACM Trans on Reconfigurable Techno. and systems, 2, article 8.
    • (2009) ACM Trans on Reconfigurable Techno. and Systems , vol.2
    • Zhao, W.S.1
  • 31
    • 77953340455 scopus 로고    scopus 로고
    • Non-volatile run-time field programmable gate arrays structures using thermally assisted switching magnetic random access memories
    • Guillemenet, Y et al., 2010, "Non-volatile run-time fieldprogrammable gate arrays structures using thermally assisted switching magnetic random access memories, " Computers & Digital Techniques, IET, vol.4, no.3, pp.211-226.
    • (2010) Computers & Digital Techniques, IET , vol.4 , Issue.3 , pp. 211-226
    • Guillemenet, Y.1
  • 32
    • 38949176844 scopus 로고    scopus 로고
    • Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: Stochastic versus deterministic aspects
    • T. Devolder et al., 2008, "Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: Stochastic versus deterministic aspects", Physic. Rev. Lett.Vol.100, 057206.
    • (2008) Physic. Rev. Lett. , vol.100 , pp. 057206
    • Devolder, T.1
  • 33
  • 34
    • 70350616352 scopus 로고    scopus 로고
    • High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits
    • Zhao, W S et al., 2009, "High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits" IEEE Transaction on Magnetics, 45, pp.3784-3787.
    • (2009) IEEE Transaction on Magnetics , vol.45 , pp. 3784-3787
    • Zhao, W.S.1
  • 37
    • 73549095981 scopus 로고    scopus 로고
    • Non-adiabatic spin-torques in narrow magnetic domain walls
    • Burrowes, C et al., 2010, "Non-adiabatic spin-torques in narrow magnetic domain walls", Nature Physics, Vol.6, pp.17- 21.
    • (2010) Nature Physics , vol.6 , pp. 17-21
    • Burrowes, C.1
  • 39
    • 79957777728 scopus 로고    scopus 로고
    • A dynamic reconfigurable MRAM based FPGA
    • Las Vegas, USA
    • Torres, L, Guillemenet, Y, Ahmed, S, Z, 2010, "A Dynamic Reconfigurable MRAM based FPGA", ERSA 2010, Las Vegas, USA, pp. 31-40.
    • (2010) ERSA 2010 , pp. 31-40
    • Torres, L.1    Guillemenet, Y.2    Ahmed, S.Z.3
  • 42
    • 57649087959 scopus 로고    scopus 로고
    • Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions
    • Matsunaga S et al., 2008, "Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions", Appl. Phys. Express, 1, 091301.
    • (2008) Appl. Phys. Express , vol.1 , pp. 091301
    • Matsunaga, S.1
  • 45
    • 24644506125 scopus 로고    scopus 로고
    • Allwood, D A et al., 2005, Science, Vol.309, pp.1688-1692.
    • (2005) Science , vol.309 , pp. 1688-1692
    • Allwood, D.A.1
  • 46
    • 64949106457 scopus 로고    scopus 로고
    • Novel architecture of the 3D Stacked MRAM L2 Cache for CMPs
    • Sun, G Y, et al., 2009, "Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs" Procs. Of HPCA, pp.239-249.
    • (2009) Procs. of HPCA , pp. 239-249
    • Sun, G.Y.1
  • 47
    • 78149253543 scopus 로고    scopus 로고
    • Low power, high reliability magnetic flip-flop
    • Lakys Y, et al., 2010, "low power, high reliability magnetic flip-flop", Electronics letters, Vol.46, pp.1493-1494.
    • (2010) Electronics Letters , vol.46 , pp. 1493-1494
    • Lakys, Y.1
  • 48
    • 79951742214 scopus 로고    scopus 로고
    • Improving the reliability of a FPGA using fault- tolerance mechanism based on magnetic memory (MRAM)
    • Aruba, Mexico
    • Cargnini, L.V, Guillemenet, Y, Torres, L and Sassatelli, G, 2010, "Improving the Reliability of a FPGA using Fault- Tolerance Mechanism Based on Magnetic Memory (MRAM)", ReConFiG, Aruba, Mexico.
    • (2010) ReConFiG
    • Cargnini, L.V.1    Guillemenet, Y.2    Torres, L.3    Sassatelli, G.4
  • 49
    • 84977098754 scopus 로고    scopus 로고
    • Embedded STT-MRAM for mobile applications: Enabling advanced chip architectures
    • Kang, S. H., 2010, "Embedded STT-MRAM for Mobile Applications: Enabling Advanced Chip Architectures", Non-Volatile Memories Workshop, UCSD.
    • (2010) Non-Volatile Memories Workshop, UCSD
    • Kang, S.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.