Design of embedded MRAM macros for memory-in-logic applications

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 155-158

  Chaudhuri, Sumanta ^a,b   Zhao, Weisheng ^a,b   Klein, Jacques Olivier ^a,b   Chappert, Claude ^a,b   Mazoyer, Pascale ^c  

^a CNRS   (France)

^b UNIVERSITÉ PARIS SACLAY   (France)

^c STMICROELECTRONICS   (France)

Author keywords

architecture; embedded; low power; mram; non volatile; system on chip (soc); thermally assisted switching (tas)

Indexed keywords

3-D INTEGRATION; AUTOMATIC FLOW; AUTOMATIC GENERATION; DESIGN METHOD; DESIGN SPACE EXPLORATION; DESIGN SPACES; GENERAL PURPOSE; LOGIC APPLICATIONS; LOW POWER; MEMORY CELL; MRAM; NON-VOLATILE; STANDARD CELL; STANDARD CMOS; SYSTEM ON CHIPS; TRANSIENT SIMULATION;

ELECTRIC BATTERIES; INTEGRATION; LAKES; MACROS; MAGNETIC STORAGE; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; SPACE RESEARCH;

DESIGN;

EID: 77954521173     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785519     Document Type: Conference Paper

References (22)

1. J. G. Zhu. Proceedings of the IEEE, 96:1786-1798, 2008.
2. B. N. Engel, et al., Magnetics, IEEE Transactions on, vol. 41, pp. 132-136, 2005.
3. W.J Gallagher. and S.S.P Parkin. IBM Journal of Research and Development, pp.5-23, 2006.
4. J. C. Slonczewski, Journal of Magnetism and Magnetic Materials, vol. 159, pp. L1-L7, June 1996.
5. J.Z Sun. IBM Journal of Research and Development, pp.81-100., 2006
6. I. L. Prejbeanu et al., IEEE Trans. on Magnetics, Vol. 40, pp. 2625-2627, 2004.
7. O. Redon et al., Proceedings of ICMTD, France, pp. 113-114, 2005.
8. R. Nebashi et al. ISSCC Technical Digest, USA, 2009.
9. M. Hosomi et al., Digest of IEDM, USA, pp.473-476., 2005
10. T. Kawahara et al., Proc of ISSCC Technical Digest, 2007.
11. J.U. Knickerbocker et al. Proc of 58th ECTC Conference, USA, 2008
12. X. Dong et al., Proc of IEEE/ACM DAC, 2008.
13. W.S. Zhao et al., "TAS-MRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA", ACM Transactions on Reconfigurable Technology and systems, Vol.2, No.2, article 8, 2009.
14. S. Matsunaga, et al., Applied Physics Express. Vol.1, Issue: 2, 023004, 2009.
15. W.S. Zhao et al., "High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits" IEEE Transaction on Magnetics, Vol.45, pp.3784-3787, 2009.
16. STMicroelectronic CMOS 65nm General Power Design Rule Manual, 2008.
17. STMicroelectronic CMOS 130nm General Power Design Rule Manual, 2007.
18. M. El Baraji et al., Journal of Applied Physics, 123906, 2010.
19. W.S. Zhao et al., "Spin Transfer Torque (STT)-MRAM based Run Time Reconfiguration FPGA circuit "ACM Transactions on Embedded Computing Systems, Vol.9, No.2, article 14, October 2009.
20. Cadence Encounter 4.1 user guide, 2006.
21. W.S. Zhao et al., "Spin-MTJ based Non-Volatile Flip-Flop" Proc. of IEEE-NANO, pp. 399-402, 2007.
22. J.H.Jung et al., Appl. Phys. Lett, Vol.96, 042503, 2010.