Architecture of a self-checkpointing microprocessor that incorporates nanomagnetic devices

IEEE Transactions on Computers

Volumn 56, Issue 2, 2007, Pages 161-173

  Kothari, Love ^a   Carter, Nicholas P ^b  

^a INTEL CORPORATION   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Emerging technologies; Low power design; Memory technologies

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; DATA STORAGE EQUIPMENT; FLIP FLOP CIRCUITS; MAGNETIC DEVICES;

MAGNETOELECTRONIC DEVICE; MEMORY TECHNOLOGY; SELF-CHECKPOINTING MICROPROCESSOR;

MICROPROCESSOR CHIPS;

EID: 33846063267     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.21     Document Type: Article

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