A novel architecture of the 3D stacked MRAM L2 Cache for CMPs

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 239-249

  Sun, Guangyu ^a   Dong, Xiangyu ^a   Xie, Yuan ^a   Li, Jian ^b   Chen, Yiran ^c  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c SEAGATE TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MAGNETIC RECORDING; MEMORY ARCHITECTURE; MRAM DEVICES; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3D HETEROGENEOUS INTEGRATION; CHIP PERFORMANCE; CONVENTIONAL CHIP MULTIPROCESSORS; CONVENTIONAL SRAM; COST-EFFICIENT; MAGNETIC RANDOM ACCESS MEMORY; MEMORY TECHNOLOGY; NOVEL ARCHITECTURE;

MAGNETIC STORAGE;

EID: 64949106457     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798259     Document Type: Conference Paper

References (27)

1. http://parsec.cs.princeton.edu/.
2. http://www.hpl.hp.com/research/cacti/.
3. http://www.spec.org/.
4. B. Black, M. Annavaram, N. Brekelbaum, et al. Die Stacking (3D) Microarchitecture. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 469-479, 2006.
5. S. Borkar. 3D Technology: A System Perspective. In Technical Digest of the International 3D System Integration Conference, pages 1-14, 2008.
6. D. Burger, J. R. Goodman, and A. Kagi. Limited Bandwidth to Affect Processor Design. Micro, IEEE, 17(6):55- 62, 1997.
7. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Optimizing Replication, Communication, and Capacity Allocation in CMPs. SIGARCH Comput. Archit. News, 33(2):357-368, 2005.
8. J. D. Davis, J. Laudon, and K. Olukotun. Maximizing CMP Throughput with Mediocre Cores. In PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 51-62, 2005.
9. W. R. Davis, J.Wilson, S.Mick, et al. Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design and Test of Computers, 22(6):498-510, 2005.
10. R. Desikan, C. R. Lefurgy, S. W. Keckler, and D. Burger. On-chip MRAM as a High-Bandwidth Low-Latency Replacement for DRAM Physical Memories. Technical report, 2002.
11. Z. Diao, Z. Li, S.Wang, et al. Spin-Transfer Torque Switching in Magnetic Tunnel Junctions and Spin-Transfer Torque Random Access Memory. Journal of Physics: Condensed Matter, 19(16):165209 (13pp), 2007.
12. X. Dong, X.Wu, G. Sun, et al. Circuit andMicroarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement. In DAC '08: Proceedings of the 45th annual conference on Design automation, pages 554-559, 2008.
13. M. Ghosh and H.-H. S. Lee. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. In MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pages 134-145, 2007.
14. M. Hosomi, H. Yamagishi, T. Yamamoto, et al. A Novel Non-Volatile Memory With Spin Torque Transfer Magnetization Switching: Spin-RAM. In International Electron Devices Meeting, pages 459-462, 2005.
15. P. Jacob, O. Erdogan, A. Zia, et al. Predicting the Performance of a 3D Processor-Memory Chip Stack. IEEE Design and Test of Computers, 22(6):540-547, 2005.
16. J. A. Kahle, M. N. Day, H. P. Hofstee, et al. Introduction to the Cell Multiprocessor. IBM Journal of Research and Development, 49(4/5):589-604, 2005.
17. T. Kgil, S. D'Souza, A. Saidi, et al. PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient ChipMultiprocessor. In Proc. the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, number 11, pages 117-128, 2006.
18. C. Kim, D. Burger, and S. Keckler. An Adaptive, Non- Uniform Cache Structure for Wire-Delay Dominated On- Chip Caches. In Proc. the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002.
19. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded SPARC Processor. IEEE Micro, 25(2):21-29, 2005.
20. F. Li, C. Nicopoulos, T. Richardson, et al. Design and Management of 3D Chip Multiprocessors Using Networkin- Memory. In ISCA '06: Proceedings of the 33rd Annual International Symposium on Computer Architecture, pages 130-141, 2006.
21. C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari. Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design and Test of Computers, 22(6):556-564, 2005.
22. G. H. Loh. 3D-Stacked Memory Architectures for Multicore Processors. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 453-464, 2008.
23. G. L. Loi, B. Agrawal, N. Srivastava, et al. A Thermally- Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy. In DAC '06: Proceedings of the 43rd Annual Conference on Design automation, pages 991-996, 2006.
24. P. S.Magnusson, M. Christensson, J. Eskilson, et al. Simics: A Full System Simulation Platform. Computer, 35(2):50- 58, 2002.
25. Y.-F. Tsai, Y. Xie, N. Vijaykrishnan, and M. J. Irwin. Three- Dimensional Cache Design Exploration Using 3DCacti. In ICCD '05: Proceedings of the 2005 International Conference on Computer Design, pages 519-524, 2005.
26. Y. Xie, G. H. Loh, B. Black, and K. Bernstein. Design Space Exploration for 3D Architectures. ACM Journal on Emerging Technologies in Computing Systems, 2(2):65-103, 2006.
27. W. Zhao, E. Belhaire, Q. Mistral, et al. Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction Device for Hybrid Magnetic-CMOS Design. In IEEE International Behavioral Modeling and Simulation Workshop, pages 40-43, 2006.